reserv.hif

采用高速A_D的存储示波器设计 在quartus2 中用的 用vhdl语言写的

DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
18
PARAMETER_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_gv7
PARAMETER_UNKNOWN
USR
}
# used_port {
aclr
clk_en
clock
q0
q1
q2
q3
q4
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|lpm_constant.inc
1081478554
e:|altera|quartus41|libraries|megafunctions|lpm_decode.inc
1081478592
e:|altera|quartus41|libraries|megafunctions|lpm_add_sub.inc
1081478464
e:|altera|quartus41|libraries|megafunctions|cmpconst.inc
1081478088
e:|altera|quartus41|libraries|megafunctions|lpm_compare.inc
1081478538
e:|altera|quartus41|libraries|megafunctions|lpm_counter.inc
1081478574
e:|altera|quartus41|libraries|megafunctions|dffeea.inc
1081478268
e:|altera|quartus41|libraries|megafunctions|alt_synch_counter.inc
1081477038
e:|altera|quartus41|libraries|megafunctions|alt_synch_counter_f.inc
1081477054
e:|altera|quartus41|libraries|megafunctions|alt_counter_f10ke.inc
1081476700
e:|altera|quartus41|libraries|megafunctions|alt_counter_stratix.inc
1081476712
e:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
cntr_gv7
# case_insensitive
# source_file
db|cntr_gv7.tdf
1126923318
6
# storage
db|RESERV.(43).cnf
db|RESERV.(43).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
}
# end
# entity
lpm_counter
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|lpm_counter.tdf
1088009428
6
# storage
db|RESERV.(44).cnf
db|RESERV.(44).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
11
PARAMETER_DEC
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
LPM_MODULUS
2048
PARAMETER_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_ln7
PARAMETER_UNKNOWN
USR
}
# used_port {
aclr
clk_en
clock
q0
q10
q1
q2
q3
q4
q5
q6
q7
q8
q9
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|lpm_constant.inc
1081478554
e:|altera|quartus41|libraries|megafunctions|lpm_decode.inc
1081478592
e:|altera|quartus41|libraries|megafunctions|lpm_add_sub.inc
1081478464
e:|altera|quartus41|libraries|megafunctions|cmpconst.inc
1081478088
e:|altera|quartus41|libraries|megafunctions|lpm_compare.inc
1081478538
e:|altera|quartus41|libraries|megafunctions|lpm_counter.inc
1081478574
e:|altera|quartus41|libraries|megafunctions|dffeea.inc
1081478268
e:|altera|quartus41|libraries|megafunctions|alt_synch_counter.inc
1081477038
e:|altera|quartus41|libraries|megafunctions|alt_synch_counter_f.inc
1081477054
e:|altera|quartus41|libraries|megafunctions|alt_counter_f10ke.inc
1081476700
e:|altera|quartus41|libraries|megafunctions|alt_counter_stratix.inc
1081476712
e:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
cntr_ln7
# case_insensitive
# source_file
db|cntr_ln7.tdf
1126923318
6
# storage
db|RESERV.(45).cnf
db|RESERV.(45).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|lpm_shiftreg.tdf
1088009432
6
# storage
db|RESERV.(46).cnf
db|RESERV.(46).cnf
# user_parameter {
LPM_WIDTH
18
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
data0
data10
data11
data12
data13
data14
data15
data16
data17
data1
data2
data3
data4
data5
data6
data7
data8
data9
enable
load
shiftin
shiftout
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|lpm_constant.inc
1081478554
e:|altera|quartus41|libraries|megafunctions|dffeea.inc
1081478268
e:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|lpm_shiftreg.tdf
1088009432
6
# storage
db|RESERV.(47).cnf
db|RESERV.(47).cnf
# user_parameter {
LPM_WIDTH
23
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
data0
data10
data11
data12
data13
data14
data15
data16
data17
data18
data19
data1
data20
data21
data22
data2
data3
data4
data5
data6
data7
data8
data9
enable
load
shiftin
shiftout
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|lpm_constant.inc
1081478554
e:|altera|quartus41|libraries|megafunctions|dffeea.inc
1081478268
e:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
sld_rom_sr
# architecture
A:INFO_REG
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|sld_rom_sr.vhd
1088009284
4
# storage
db|RESERV.(48).cnf
db|RESERV.(48).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
32
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
}
# end
# entity
sld_hub
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|sld_hub.vhd
1088009286
4
# storage
db|RESERV.(49).cnf
db|RESERV.(49).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
1
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Cyclone
PARAMETER_UNKNOWN
USR
n_nodes
2
PARAMETER_UNKNOWN
USR
n_sel_bits
2
PARAMETER_UNKNOWN
USR
n_node_ir_bits
7
PARAMETER_UNKNOWN
USR
node_info
0001100000000000011011100000000000000000000110000110111000000000
PARAMETER_BIN
USR
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
}
# end
# entity
sld_jtag_state_machine
# architecture
A:rtl
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|sld_hub.vhd
1088009286
4
# storage
db|RESERV.(50).cnf
db|RESERV.(50).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# user_parameter {
ip_major_version
1
PARAMETER_DEC
USR
ip_minor_version
1
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|lpm_shiftreg.tdf
1088009432
6
# storage
db|RESERV.(51).cnf
db|RESERV.(51).cnf
# user_parameter {
LPM_WIDTH
10
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
enable
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
shiftin
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|lpm_constant.inc
1081478554
e:|altera|quartus41|libraries|megafunctions|dffeea.inc
1081478268
e:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
lpm_decode
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|lpm_decode.tdf
1088009430
6
# storage
db|RESERV.(52).cnf
db|RESERV.(52).cnf
# user_parameter {
LPM_WIDTH
3
PARAMETER_DEC
USR
LPM_DECODES
8
PARAMETER_DEC
USR
LPM_PIPELINE
1
PARAMETER_DEC
USR
CASCADE_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
decode_9ie
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq7
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|declut.inc
1081478244
e:|altera|quartus41|libraries|megafunctions|altshift.inc
1081477602
e:|altera|quartus41|libraries|megafunctions|lpm_compare.inc
1081478538
e:|altera|quartus41|libraries|megafunctions|lpm_constant.inc
1081478554
e:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
decode_9ie
# case_insensitive
# source_file
db|decode_9ie.tdf
1126923320
6
# storage
db|RESERV.(53).cnf
db|RESERV.(53).cnf
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq4
eq5
eq6
eq7
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|sld_dffex.vhd
1088009286
4
# storage
db|RESERV.(54).cnf
db|RESERV.(54).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# user_parameter {
size
1
PARAMETER_DEC
USR
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_hub.vhd
1088009286
e:|altera|quartus41|libraries|megafunctions|sld_hub.vhd
1088009286
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|sld_dffex.vhd
1088009286
4
# storage
db|RESERV.(55).cnf
db|RESERV.(55).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# user_parameter {
size
9
PARAMETER_DEC
USR
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_hub.vhd
1088009286
e:|altera|quartus41|libraries|megafunctions|sld_hub.vhd
1088009286
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|sld_dffex.vhd
1088009286
4
# storage
db|RESERV.(56).cnf
db|RESERV.(56).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# user_parameter {
size
7
PARAMETER_DEC
USR
}
# include_file {
e:|altera|quartus41