reserv.hif

采用高速A_D的存储示波器设计 在quartus2 中用的 用vhdl语言写的

Version 4.1 Build 181 06/29/2004 SJ Full Version
31
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# entity
RESERV
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
RESERV.VHD
1122871932
4
# storage
db|RESERV.(0).cnf
db|RESERV.(0).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
DPRAM
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
DPRAM.vhd
1107053122
4
# storage
db|RESERV.(1).cnf
db|RESERV.(1).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
altsyncram
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|altsyncram.tdf
1088009418
6
# storage
db|RESERV.(2).cnf
db|RESERV.(2).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
SINGLE_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
10
PARAMETER_DEC
USR
NUMWORDS_A
1024
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
M4K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
./DATA/LUT8X10.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
1024
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_d071
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
wren_a
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|stratix_ram_block.inc
1081479498
e:|altera|quartus41|libraries|megafunctions|lpm_mux.inc
1081478758
e:|altera|quartus41|libraries|megafunctions|lpm_decode.inc
1081478592
e:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
e:|altera|quartus41|libraries|megafunctions|altsyncram.inc
1081477654
e:|altera|quartus41|libraries|megafunctions|a_rdenreg.inc
1081476578
e:|altera|quartus41|libraries|megafunctions|altrom.inc
1081477590
e:|altera|quartus41|libraries|megafunctions|altram.inc
1081477560
e:|altera|quartus41|libraries|megafunctions|altdpram.inc
1081477328
e:|altera|quartus41|libraries|megafunctions|altqpram.inc
1081477546
}
# end
# entity
altsyncram_d071
# case_insensitive
# source_file
db|altsyncram_d071.tdf
1126923310
6
# storage
db|RESERV.(3).cnf
db|RESERV.(3).cnf
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# end
# entity
altsyncram_56e2
# case_insensitive
# source_file
db|altsyncram_56e2.tdf
1126923310
6
# storage
db|RESERV.(4).cnf
db|RESERV.(4).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
address_b9
clock0
clock1
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_b0
data_b1
data_b2
data_b3
data_b4
data_b5
data_b6
data_b7
wren_a
wren_b
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
}
# memory_file {
.|DATA|LUT8X10.mif
1088982184
}
# end
# entity
sld_mod_ram_rom
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
4
# storage
db|RESERV.(5).cnf
db|RESERV.(5).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# user_parameter {
sld_node_info
1601024
PARAMETER_DEC
DEF
sld_ip_version
0
PARAMETER_DEC
DEF
sld_ip_minor_version
0
PARAMETER_DEC
DEF
sld_common_ip_version
0
PARAMETER_DEC
DEF
width_word
8
PARAMETER_UNKNOWN
USR
numwords
1024
PARAMETER_UNKNOWN
USR
widthad
10
PARAMETER_UNKNOWN
USR
shift_count_bits
4
PARAMETER_UNKNOWN
USR
cvalue
00000000
PARAMETER_UNKNOWN
USR
is_data_in_ram
1
PARAMETER_UNKNOWN
USR
is_readable
1
PARAMETER_UNKNOWN
USR
node_name
1918987629
PARAMETER_UNKNOWN
USR
}
# end
# entity
sld_rom_sr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|sld_rom_sr.vhd
1088009284
4
# storage
db|RESERV.(6).cnf
db|RESERV.(6).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
80
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
}
# end
# entity
sld_signaltap
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
4
# storage
db|RESERV.(7).cnf
db|RESERV.(7).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# user_parameter {
sld_node_info
402681344
PARAMETER_UNKNOWN
USR
sld_ip_version
3
PARAMETER_DEC
DEF
sld_ip_minor_version
1
PARAMETER_DEC
DEF
sld_common_ip_version
0
PARAMETER_DEC
DEF
sld_data_bits
18
PARAMETER_UNKNOWN
USR
sld_trigger_bits
18
PARAMETER_UNKNOWN
USR
sld_data_bit_cntr_bits
5
PARAMETER_UNKNOWN
USR
sld_node_crc_bits
32
PARAMETER_DEC
DEF
sld_node_crc_hiword
40495
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
44617
PARAMETER_UNKNOWN
USR
sld_incremental_routing
0
PARAMETER_DEC
DEF
sld_sample_depth
2048
PARAMETER_UNKNOWN
USR
sld_mem_address_bits
11
PARAMETER_UNKNOWN
USR
sld_ram_block_type
M4K
PARAMETER_UNKNOWN
USR
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
1
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_2
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_3
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_4
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_5
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_6
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_7
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_8
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_9
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_10
NONE
PARAMETER_STRING
DEF
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
}
# end
# entity
sld_ela_control
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|sld_ela_control.vhd
1088009286
4
# storage
db|RESERV.(8).cnf
db|RESERV.(8).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# user_parameter {
ip_major_version
3
PARAMETER_DEC
USR
ip_minor_version
1
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
trigger_input_width
18
PARAMETER_DEC
USR
trigger_level
1
PARAMETER_DEC
USR
trigger_in_enabled
1
PARAMETER_DEC
USR
enable_clk_edge_def
0
PARAMETER_DEC
USR
enable_async_glitch
0
PARAMETER_DEC
USR
enable_sync_normal
1
PARAMETER_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_DEC
USR
trigger_level_pipeline
1
PARAMETER_DEC
USR
ela_status_bits
3
PARAMETER_DEC
USR
mem_address_bits
11
PARAMETER_DEC
USR
sample_depth
2048
PARAMETER_DEC
USR
}
# include_file {
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
e:|altera|quartus41|libraries|megafunctions|sld_signaltap.vhd
1088009288
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
e:|altera|quartus41|libraries|megafunctions|lpm_shiftreg.tdf
1088009432
6
# storage
db|RESERV.(9).cnf
db|RESERV.(9).cnf
# user_parameter {
LPM_WIDTH
20
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
data0
data10
data11
data12
data13
data14
data15
data16
data17
data18
data19
data1
data2
data3
data4
data5
data6
data7
data8
data9
enable
load
q0
q10
q11
q12
q13
q14
q15
q16
q17
q18
q19
q1
q2
q3
q4
q5
q6
q7
q8
q9
shiftin
shiftout
}