reserv.hier_info

采用高速A_D的存储示波器设计 在quartus2 中用的 用vhdl语言写的

|RESERV
CLK => Q1[8].CLK
CLK => Q1[7].CLK
CLK => Q1[6].CLK
CLK => Q1[5].CLK
CLK => Q1[4].CLK
CLK => Q1[3].CLK
CLK => Q1[2].CLK
CLK => Q1[1].CLK
CLK => Q1[0].CLK
CLK => DIN[7].CLK
CLK => DIN[6].CLK
CLK => DIN[5].CLK
CLK => DIN[4].CLK
CLK => DIN[3].CLK
CLK => DIN[2].CLK
CLK => DIN[1].CLK
CLK => DIN[0].CLK
CLK => DPRAM:u1.inclock
CLK => Q1[9].CLK
CLK => AD_CLK.DATAIN
CLK => DA_CLK.DATAIN
KEY1 => DPRAM:u1.wren
DA_CLK <= CLK.DB_MAX_OUTPUT_PORT_TYPE
AD_CLK <= CLK.DB_MAX_OUTPUT_PORT_TYPE
TRAG[0] <= Q1[0].DB_MAX_OUTPUT_PORT_TYPE
TRAG[1] <= Q1[1].DB_MAX_OUTPUT_PORT_TYPE
TRAG[2] <= Q1[2].DB_MAX_OUTPUT_PORT_TYPE
TRAG[3] <= Q1[3].DB_MAX_OUTPUT_PORT_TYPE
TRAG[4] <= Q1[4].DB_MAX_OUTPUT_PORT_TYPE
TRAG[5] <= Q1[5].DB_MAX_OUTPUT_PORT_TYPE
TRAG[6] <= Q1[6].DB_MAX_OUTPUT_PORT_TYPE
TRAG[7] <= Q1[7].DB_MAX_OUTPUT_PORT_TYPE
TRAG[8] <= Q1[8].DB_MAX_OUTPUT_PORT_TYPE
TRAG[9] <= Q1[9].DB_MAX_OUTPUT_PORT_TYPE
DOUT[0] <= <GND>
DOUT[1] <= <GND>
DOUT[2] <= DPRAM:u1.q[0]
DOUT[3] <= DPRAM:u1.q[1]
DOUT[4] <= DPRAM:u1.q[2]
DOUT[5] <= DPRAM:u1.q[3]
DOUT[6] <= DPRAM:u1.q[4]
DOUT[7] <= DPRAM:u1.q[5]
DOUT[8] <= DPRAM:u1.q[6]
DOUT[9] <= DPRAM:u1.q[7]
ADIN[0] => DIN[0].DATAIN
ADIN[1] => DIN[1].DATAIN
ADIN[2] => DIN[2].DATAIN
ADIN[3] => DIN[3].DATAIN
ADIN[4] => DIN[4].DATAIN
ADIN[5] => DIN[5].DATAIN
ADIN[6] => DIN[6].DATAIN
ADIN[7] => DIN[7].DATAIN


|RESERV|DPRAM:u1
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
inclock => altsyncram:altsyncram_component.clock0
data[0] => altsyncram:altsyncram_component.data_a[0]
data[1] => altsyncram:altsyncram_component.data_a[1]
data[2] => altsyncram:altsyncram_component.data_a[2]
data[3] => altsyncram:altsyncram_component.data_a[3]
data[4] => altsyncram:altsyncram_component.data_a[4]
data[5] => altsyncram:altsyncram_component.data_a[5]
data[6] => altsyncram:altsyncram_component.data_a[6]
data[7] => altsyncram:altsyncram_component.data_a[7]
wren => altsyncram:altsyncram_component.wren_a
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|RESERV|DPRAM:u1|altsyncram:altsyncram_component
wren_a => altsyncram_d071:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_d071:auto_generated.data_a[0]
data_a[1] => altsyncram_d071:auto_generated.data_a[1]
data_a[2] => altsyncram_d071:auto_generated.data_a[2]
data_a[3] => altsyncram_d071:auto_generated.data_a[3]
data_a[4] => altsyncram_d071:auto_generated.data_a[4]
data_a[5] => altsyncram_d071:auto_generated.data_a[5]
data_a[6] => altsyncram_d071:auto_generated.data_a[6]
data_a[7] => altsyncram_d071:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_d071:auto_generated.address_a[0]
address_a[1] => altsyncram_d071:auto_generated.address_a[1]
address_a[2] => altsyncram_d071:auto_generated.address_a[2]
address_a[3] => altsyncram_d071:auto_generated.address_a[3]
address_a[4] => altsyncram_d071:auto_generated.address_a[4]
address_a[5] => altsyncram_d071:auto_generated.address_a[5]
address_a[6] => altsyncram_d071:auto_generated.address_a[6]
address_a[7] => altsyncram_d071:auto_generated.address_a[7]
address_a[8] => altsyncram_d071:auto_generated.address_a[8]
address_a[9] => altsyncram_d071:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_d071:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_d071:auto_generated.q_a[0]
q_a[1] <= altsyncram_d071:auto_generated.q_a[1]
q_a[2] <= altsyncram_d071:auto_generated.q_a[2]
q_a[3] <= altsyncram_d071:auto_generated.q_a[3]
q_a[4] <= altsyncram_d071:auto_generated.q_a[4]
q_a[5] <= altsyncram_d071:auto_generated.q_a[5]
q_a[6] <= altsyncram_d071:auto_generated.q_a[6]
q_a[7] <= altsyncram_d071:auto_generated.q_a[7]
q_b[0] <= <UNC>


|RESERV|DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated
address_a[0] => altsyncram_56e2:altsyncram1.address_a[0]
address_a[1] => altsyncram_56e2:altsyncram1.address_a[1]
address_a[2] => altsyncram_56e2:altsyncram1.address_a[2]
address_a[3] => altsyncram_56e2:altsyncram1.address_a[3]
address_a[4] => altsyncram_56e2:altsyncram1.address_a[4]
address_a[5] => altsyncram_56e2:altsyncram1.address_a[5]
address_a[6] => altsyncram_56e2:altsyncram1.address_a[6]
address_a[7] => altsyncram_56e2:altsyncram1.address_a[7]
address_a[8] => altsyncram_56e2:altsyncram1.address_a[8]
address_a[9] => altsyncram_56e2:altsyncram1.address_a[9]
clock0 => altsyncram_56e2:altsyncram1.clock0
data_a[0] => altsyncram_56e2:altsyncram1.data_a[0]
data_a[1] => altsyncram_56e2:altsyncram1.data_a[1]
data_a[2] => altsyncram_56e2:altsyncram1.data_a[2]
data_a[3] => altsyncram_56e2:altsyncram1.data_a[3]
data_a[4] => altsyncram_56e2:altsyncram1.data_a[4]
data_a[5] => altsyncram_56e2:altsyncram1.data_a[5]
data_a[6] => altsyncram_56e2:altsyncram1.data_a[6]
data_a[7] => altsyncram_56e2:altsyncram1.data_a[7]
q_a[0] <= altsyncram_56e2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_56e2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_56e2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_56e2:altsyncram1.q_a[3]
q_a[4] <= altsyncram_56e2:altsyncram1.q_a[4]
q_a[5] <= altsyncram_56e2:altsyncram1.q_a[5]
q_a[6] <= altsyncram_56e2:altsyncram1.q_a[6]
q_a[7] <= altsyncram_56e2:altsyncram1.q_a[7]
wren_a => altsyncram_56e2:altsyncram1.wren_a


|RESERV|DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_a[8] => ram_block3a0.PORTAADDR8
address_a[8] => ram_block3a1.PORTAADDR8
address_a[8] => ram_block3a2.PORTAADDR8
address_a[8] => ram_block3a3.PORTAADDR8
address_a[8] => ram_block3a4.PORTAADDR8
address_a[8] => ram_block3a5.PORTAADDR8
address_a[8] => ram_block3a6.PORTAADDR8
address_a[8] => ram_block3a7.PORTAADDR8
address_a[9] => ram_block3a0.PORTAADDR9
address_a[9] => ram_block3a1.PORTAADDR9
address_a[9] => ram_block3a2.PORTAADDR9
address_a[9] => ram_block3a3.PORTAADDR9
address_a[9] => ram_block3a4.PORTAADDR9
address_a[9] => ram_block3a5.PORTAADDR9
address_a[9] => ram_block3a6.PORTAADDR9
address_a[9] => ram_block3a7.PORTAADDR9
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2
address_b[2] => ram_block3a7.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[3] => ram_block3a4.PORTBADDR3
address_b[3] => ram_block3a5.PORTBADDR3
address_b[3] => ram_block3a6.PORTBADDR3
address_b[3] => ram_block3a7.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[4] => ram_block3a4.PORTBADDR4
address_b[4] => ram_block3a5.PORTBADDR4
address_b[4] => ram_block3a6.PORTBADDR4
address_b[4] => ram_block3a7.PORTBADDR4
address_b[5] => ram_block3a0.PORTBADDR5
address_b[5] => ram_block3a1.PORTBADDR5
address_b[5] => ram_block3a2.PORTBADDR5
address_b[5] => ram_block3a3.PORTBADDR5
address_b[5] => ram_block3a4.PORTBADDR5
address_b[5] => ram_block3a5.PORTBADDR5
address_b[5] => ram_block3a6.PORTBADDR5
address_b[5] => ram_block3a7.PORTBADDR5
address_b[6] => ram_block3a0.PORTBADDR6
address_b[6] => ram_block3a1.PORTBADDR6
address_b[6] => ram_block3a2.PORTBADDR6
address_b[6] => ram_block3a3.PORTBADDR6
address_b[6] => ram_block3a4.PORTBADDR6
address_b[6] => ram_block3a5.PORTBADDR6
address_b[6] => ram_block3a6.PORTBADDR6
address_b[6] => ram_block3a7.PORTBADDR6
address_b[7] => ram_block3a0.PORTBADDR7
address_b[7] => ram_block3a1.PORTBADDR7
address_b[7] => ram_block3a2.PORTBADDR7
address_b[7] => ram_block3a3.PORTBADDR7
address_b[7] => ram_block3a4.PORTBADDR7
address_b[7] => ram_block3a5.PORTBADDR7
address_b[7] => ram_block3a6.PORTBADDR7
address_b[7] => ram_block3a7.PORTBADDR7
address_b[8] => ram_block3a0.PORTBADDR8
address_b[8] => ram_block3a1.PORTBADDR8
address_b[8] => ram_block3a2.PORTBADDR8
address_b[8] => ram_block3a3.PORTBADDR8
address_b[8] => ram_block3a4.PORTBADDR8
address_b[8] => ram_block3a5.PORTBADDR8
address_b[8] => ram_block3a6.PORTBADDR8
address_b[8] => ram_block3a7.PORTBADDR8
address_b[9] => ram_block3a0.PORTBADDR9
address_b[9] => ram_block3a1.PORTBADDR9
address_b[9] => ram_block3a2.PORTBADDR9
address_b[9] => ram_block3a3.PORTBADDR9
address_b[9] => ram_block3a4.PORTBADDR9
address_b[9] => ram_block3a5.PORTBADDR9
address_b[9] => ram_block3a6.PORTBADDR9
address_b[9] => ram_block3a7.PORTBADDR9
clock0 => ram_block3a0.CLK0
clock0 => ram_block3a1.CLK0
clock0 => ram_block3a2.CLK0
clock0 => ram_block3a3.CLK0
clock0 => ram_block3a4.CLK0
clock0 => ram_block3a5.CLK0
clock0 => ram_block3a6.CLK0
clock0 => ram_block3a7.CLK0
clock1 => ram_block3a0.CLK1
clock1 => ram_block3a1.CLK1
clock1 => ram_block3a2.CLK1
clock1 => ram_block3a3.CLK1
clock1 => ram_block3a4.CLK1
clock1 => ram_block3a5.CLK1
clock1 => ram_block3a6.CLK1
clock1 => ram_block3a7.CLK1
data_a[0] => ram_block3a0.PORTADATAIN
data_a[1] => ram_block3a1.PORTADATAIN
data_a[2] => ram_block3a2.PORTADATAIN
data_a[3] => ram_block3a3.PORTADATAIN
data_a[4] => ram_block3a4.PORTADATAIN
data_a[5] => ram_block3a5.PORTADATAIN
data_a[6] => ram_block3a6.PORTADATAIN
data_a[7] => ram_block3a7.PORTADATAIN
data_b[0] => ram_block3a0.PORTBDATAIN
data_b[1] => ram_block3a1.PORTBDATAIN
data_b[2] => ram_block3a2.PORTBDATAIN
data_b[3] => ram_block3a3.PORTBDATAIN
data_b[4] => ram_block3a4.PORTBDATAIN
data_b[5] => ram_block3a5.PORTBDATAIN
data_b[6] => ram_block3a6.PORTBDATAIN
data_b[7] => ram_block3a7.PORTBDATAIN
q_a[0] <= ram_block3a0.PORTADATAOUT
q_a[1] <= ram_block3a1.PORTADATAOUT
q_a[2] <= ram_block3a2.PORTADATAOUT
q_a[3] <= ram_block3a3.PORTADATAOUT
q_a[4] <= ram_block3a4.PORTADATAOUT
q_a[5] <= ram_block3a5.PORTADATAOUT
q_a[6] <= ram_block3a6.PORTADATAOUT
q_a[7] <= ram_block3a7.PORTADATAOUT
q_b[0] <= ram_block3a0.PORTBDATAOUT
q_b[1] <= ram_block3a1.PORTBDATAOUT
q_b[2] <= ram_block3a2.PORTBDATAOUT
q_b[3] <= ram_block3a3.PORTBDATAOUT
q_b[4] <= ram_block3a4.PORTBDATAOUT
q_b[5] <= ram_block3a5.PORTBDATAOUT
q_b[6] <= ram_block3a6.PORTBDATAOUT
q_b[7] <= ram_block3a7.PORTBDATAOUT
wren_a => ram_block3a0.PORTAWE
wren_a => ram_block3a1.PORTAWE
wren_a => ram_block3a2.PORTAWE
wren_a => ram_block3a3.PORTAWE
wren_a => ram_block3a4.PORTAWE
wren_a => ram_block3a5.PORTAWE
wren_a => ram_block3a6.PORTAWE
wren_a => ram_block3a7.PORTAWE
wren_b => ram_block3a0.PORTBRE
wren_b => ram_block3a1.PORTBRE
wren_b => ram_block3a2.PORTBRE
wren_b => ram_block3a3.PORTBRE
wren_b => ram_block3a4.PORTBRE
wren_b => ram_block3a5.PORTBRE
wren_b => ram_block3a6.PORTBRE
wren_b => ram_block3a7.PORTBRE


|RESERV|DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2
tck_usr <= raw_tck.DB_MAX_OUTPUT_PORT_TYPE
address[0] <= ram_rom_addr_reg[0].DB_MAX_OUTPUT_PORT_TYPE
address[1] <= ram_rom_addr_reg[1].DB_MAX_OUTPUT_PORT_TYPE
address[2] <= ram_rom_addr_reg[2].DB_MAX_OUTPUT_PORT_TYPE
address[3] <= ram_rom_addr_reg[3].DB_MAX_OUTPUT_PORT_TYPE
address[4] <= ram_rom_addr_reg[4].DB_MAX_OUTPUT_PORT_TYPE
address[5] <= ram_rom_addr_reg[5].DB_MAX_OUTPUT_PORT_TYPE
address[6] <= ram_rom_addr_reg[6].DB_MAX_OUTPUT_PORT_TYPE
address[7] <= ram_rom_addr_reg[7].DB_MAX_OUTPUT_PORT_TYPE
address[8] <= ram_rom_addr_reg[8].DB_MAX_OUTPUT_PORT_TYPE
address[9] <= ram_rom_addr_reg[9].DB_MAX_OUTPUT_PORT_TYPE
enable_write <= ram_rom_incr_addr~1.DB_MAX_OUTPUT_PORT_TYPE
data_write[0] <= ram_rom_data_reg[0].DB_MAX_OUTPUT_PORT_TYPE
data_write[1] <= ram_rom_data_reg[1].DB_MAX_OUTPUT_PORT_TYPE
data_write[2] <= ram_rom_data_reg[2].DB_MAX_OUTPUT_PORT_TYPE
data_write[3] <= ram_rom_data_reg[3].DB_MAX_OUTPUT_PORT_TYPE
data_write[4] <= ram_rom_data_reg[4].DB_MAX_OUTPUT_PORT_TYPE
data_write[5] <= ram_rom_data_reg[5].DB_MAX_OUTPUT_PORT_TYPE
data_write[6] <= ram_rom_data_reg[6].DB_MAX_OUTPUT_PORT_TYPE
data_write[7] <= ram_rom_data_reg[7].DB_MAX_OUTPUT_PORT_TYPE
data_read[0] => ram_rom_data_reg~15.DATAB
data_read[1] => ram_rom_data_reg~14.DATAB
data_read[2] => ram_rom_data_reg~13.DATAB
data_read[3] => ram_rom_data_reg~12.DATAB
data_read[4] => ram_rom_data_reg~11.DATAB
data_read[5] => ram_rom_data_reg~10.DATAB
data_read[6] => ram_rom_data_reg~9.DATAB
data_read[7] => ram_rom_data_reg~8.DATAB
raw_tck => ram_rom_addr_reg[8].CLK
raw_tck => ram_rom_addr_reg[7].CLK
raw_tck => ram_rom_addr_reg[6].CLK
raw_tck => ram_rom_addr_reg[5].CLK
raw_tck => ram_rom_addr_reg[4].CLK
raw_tck => ram_rom_addr_reg[3].CLK
raw_tck => ram_rom_addr_reg[2].CLK
raw_tck => ram_rom_addr_reg[1].CLK