reserv.tan.qmsg

采用高速A_D的存储示波器设计 在quartus2 中用的 用vhdl语言写的

{ "Info" "ITDB_FULL_TPD_RESULT" "CLK DA_CLK 5.226 ns Longest " "Info: Longest tpd from source pin CLK to destination pin DA_CLK is 5.226 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 317 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 317; CLK Node = 'CLK'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.633 ns) + CELL(2.124 ns) 5.226 ns DA_CLK 2 PIN PIN_167 0 " "Info: 2: + IC(1.633 ns) + CELL(2.124 ns) = 5.226 ns; Loc. = PIN_167; Fanout = 0; PIN Node = 'DA_CLK'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "3.757 ns" { CLK DA_CLK } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.593 ns 68.75 % " "Info: Total cell delay = 3.593 ns ( 68.75 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.633 ns 31.25 % " "Info: Total interconnect delay = 1.633 ns ( 31.25 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "5.226 ns" { CLK DA_CLK } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[11\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP 3.157 ns register " "Info: th for register sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[11\] (data pin = altera_internal_jtag~TMSUTAP, clock pin = altera_internal_jtag~TCKUTAP) is 3.157 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.889 ns + Longest register " "Info: + Longest clock path from clock altera_internal_jtag~TCKUTAP to destination register is 4.889 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 398 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 398; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.178 ns) + CELL(0.711 ns) 4.889 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[11\] 2 REG LC_X10_Y7_N1 12 " "Info: 2: + IC(4.178 ns) + CELL(0.711 ns) = 4.889 ns; Loc. = LC_X10_Y7_N1; Fanout = 12; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[11\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.889 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[11] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.54 % " "Info: Total cell delay = 0.711 ns ( 14.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.178 ns 85.46 % " "Info: Total interconnect delay = 4.178 ns ( 85.46 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.889 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[11] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.747 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.747 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y10_N1 22 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 22; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.438 ns) + CELL(0.309 ns) 1.747 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[11\] 2 REG LC_X10_Y7_N1 12 " "Info: 2: + IC(1.438 ns) + CELL(0.309 ns) = 1.747 ns; Loc. = LC_X10_Y7_N1; Fanout = 12; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[11\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "1.747 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[11] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 17.69 % " "Info: Total cell delay = 0.309 ns ( 17.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.438 ns 82.31 % " "Info: Total interconnect delay = 1.438 ns ( 82.31 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "1.747 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[11] } "NODE_NAME" } } }  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.889 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[11] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "1.747 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[11] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "CLK TRAG\[1\] lpm_counter:Q1_rtl_0\|cntr_pt6:auto_generated\|safe_q\[1\] 7.830 ns register " "Info: Minimum tco from clock CLK to destination pin TRAG\[1\] through register lpm_counter:Q1_rtl_0\|cntr_pt6:auto_generated\|safe_q\[1\] is 7.830 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.919 ns + Shortest register " "Info: + Shortest clock path from clock CLK to source register is 2.919 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 317 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 317; CLK Node = 'CLK'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.739 ns) + CELL(0.711 ns) 2.919 ns lpm_counter:Q1_rtl_0\|cntr_pt6:auto_generated\|safe_q\[1\] 2 REG LC_X23_Y10_N1 6 " "Info: 2: + IC(0.739 ns) + CELL(0.711 ns) = 2.919 ns; Loc. = LC_X23_Y10_N1; Fanout = 6; REG Node = 'lpm_counter:Q1_rtl_0\|cntr_pt6:auto_generated\|safe_q\[1\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "1.450 ns" { CLK lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[1] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/cntr_pt6.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/cntr_pt6.tdf" 124 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.68 % " "Info: Total cell delay = 2.180 ns ( 74.68 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.739 ns 25.32 % " "Info: Total interconnect delay = 0.739 ns ( 25.32 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "2.919 ns" { CLK lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/cntr_pt6.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/cntr_pt6.tdf" 124 8 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.687 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.687 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:Q1_rtl_0\|cntr_pt6:auto_generated\|safe_q\[1\] 1 REG LC_X23_Y10_N1 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y10_N1; Fanout = 6; REG Node = 'lpm_counter:Q1_rtl_0\|cntr_pt6:auto_generated\|safe_q\[1\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "" { lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[1] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/cntr_pt6.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/cntr_pt6.tdf" 124 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.563 ns) + CELL(2.124 ns) 4.687 ns TRAG\[1\] 2 PIN PIN_137 0 " "Info: 2: + IC(2.563 ns) + CELL(2.124 ns) = 4.687 ns; Loc. = PIN_137; Fanout = 0; PIN Node = 'TRAG\[1\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.687 ns" { lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[1] TRAG[1] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 45.32 % " "Info: Total cell delay = 2.124 ns ( 45.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.563 ns 54.68 % " "Info: Total interconnect delay = 2.563 ns ( 54.68 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.687 ns" { lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[1] TRAG[1] } "NODE_NAME" } } }  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "2.919 ns" { CLK lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[1] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.687 ns" { lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[1] TRAG[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.124 ns Shortest " "Info: Shortest tpd from source pin altera_internal_jtag~TDO to destination pin altera_reserved_tdo is 2.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y10_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.124 ns) 2.124 ns altera_reserved_tdo 2 PIN PIN_149 0 " "Info: 2: + IC(0.000 ns) + CELL(2.124 ns) = 2.124 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 100.00 % " "Info: Total cell delay = 2.124 ns ( 100.00 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } } }  } 0}