📄 reserv.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK memory DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a6~porta_address_reg0 register sld_signaltap:rsv1\|acq_trigger_in_reg\[15\] 141.16 MHz 7.084 ns Internal " "Info: Clock CLK has Internal fmax of 141.16 MHz between source memory DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a6~porta_address_reg0 and destination register sld_signaltap:rsv1\|acq_trigger_in_reg\[15\] (period= 7.084 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.416 ns + Longest memory register " "Info: + Longest memory to register delay is 6.416 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a6~porta_address_reg0 1 MEM M4K_X17_Y6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y6; Fanout = 4; MEM Node = 'DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a6~porta_address_reg0'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "" { DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a6~porta_address_reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" 243 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|q_a\[5\] 2 MEM M4K_X17_Y6 2 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X17_Y6; Fanout = 2; MEM Node = 'DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|q_a\[5\]'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.308 ns" { DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a6~porta_address_reg0 DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[5] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" 39 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.993 ns) + CELL(0.115 ns) 6.416 ns sld_signaltap:rsv1\|acq_trigger_in_reg\[15\] 3 REG LC_X22_Y12_N3 3 " "Info: 3: + IC(1.993 ns) + CELL(0.115 ns) = 6.416 ns; Loc. = LC_X22_Y12_N3; Fanout = 3; REG Node = 'sld_signaltap:rsv1\|acq_trigger_in_reg\[15\]'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "2.108 ns" { DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[5] sld_signaltap:rsv1|acq_trigger_in_reg[15] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" 512 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.423 ns 68.94 % " "Info: Total cell delay = 4.423 ns ( 68.94 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.993 ns 31.06 % " "Info: Total interconnect delay = 1.993 ns ( 31.06 % )" { } { } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "6.416 ns" { DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a6~porta_address_reg0 DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[5] sld_signaltap:rsv1|acq_trigger_in_reg[15] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.019 ns - Smallest " "Info: - Smallest clock skew is 0.019 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.919 ns + Shortest register " "Info: + Shortest clock path from clock CLK to destination register is 2.919 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 317 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 317; CLK Node = 'CLK'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.739 ns) + CELL(0.711 ns) 2.919 ns sld_signaltap:rsv1\|acq_trigger_in_reg\[15\] 2 REG LC_X22_Y12_N3 3 " "Info: 2: + IC(0.739 ns) + CELL(0.711 ns) = 2.919 ns; Loc. = LC_X22_Y12_N3; Fanout = 3; REG Node = 'sld_signaltap:rsv1\|acq_trigger_in_reg\[15\]'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "1.450 ns" { CLK sld_signaltap:rsv1|acq_trigger_in_reg[15] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" 512 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.68 % " "Info: Total cell delay = 2.180 ns ( 74.68 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.739 ns 25.32 % " "Info: Total interconnect delay = 0.739 ns ( 25.32 % )" { } { } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "2.919 ns" { CLK sld_signaltap:rsv1|acq_trigger_in_reg[15] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.900 ns - Longest memory " "Info: - Longest clock path from clock CLK to source memory is 2.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 317 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 317; CLK Node = 'CLK'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.709 ns) + CELL(0.722 ns) 2.900 ns DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a6~porta_address_reg0 2 MEM M4K_X17_Y6 4 " "Info: 2: + IC(0.709 ns) + CELL(0.722 ns) = 2.900 ns; Loc. = M4K_X17_Y6; Fanout = 4; MEM Node = 'DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a6~porta_address_reg0'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "1.431 ns" { CLK DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a6~porta_address_reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" 243 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 75.55 % " "Info: Total cell delay = 2.191 ns ( 75.55 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.709 ns 24.45 % " "Info: Total interconnect delay = 0.709 ns ( 24.45 % )" { } { } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "2.900 ns" { CLK DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a6~porta_address_reg0 } "NODE_NAME" } } } } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "2.919 ns" { CLK sld_signaltap:rsv1|acq_trigger_in_reg[15] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "2.900 ns" { CLK DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a6~porta_address_reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" 243 2 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "e:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" 512 -1 0 } } } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "6.416 ns" { DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a6~porta_address_reg0 DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[5] sld_signaltap:rsv1|acq_trigger_in_reg[15] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "2.919 ns" { CLK sld_signaltap:rsv1|acq_trigger_in_reg[15] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "2.900 ns" { CLK DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a6~porta_address_reg0 } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[1\] register sld_hub:sld_hub_inst\|HUB_TDO~reg0 114.6 MHz 8.726 ns Internal " "Info: Clock altera_internal_jtag~TCKUTAP has Internal fmax of 114.6 MHz between source register sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[1\] and destination register sld_hub:sld_hub_inst\|HUB_TDO~reg0 (period= 8.726 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.102 ns + Longest register register " "Info: + Longest register to register delay is 4.102 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[1\] 1 REG LC_X16_Y6_N6 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y6_N6; Fanout = 7; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[1\]'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.601 ns) + CELL(0.590 ns) 2.191 ns sld_hub:sld_hub_inst\|HUB_TDO~498 2 COMB LC_X16_Y7_N7 1 " "Info: 2: + IC(1.601 ns) + CELL(0.590 ns) = 2.191 ns; Loc. = LC_X16_Y7_N7; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~498'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "2.191 ns" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1] sld_hub:sld_hub_inst|HUB_TDO~498 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.292 ns) 2.933 ns sld_hub:sld_hub_inst\|HUB_TDO~517 3 COMB LC_X16_Y7_N2 1 " "Info: 3: + IC(0.450 ns) + CELL(0.292 ns) = 2.933 ns; Loc. = LC_X16_Y7_N2; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~517'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "0.742 ns" { sld_hub:sld_hub_inst|HUB_TDO~498 sld_hub:sld_hub_inst|HUB_TDO~517 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.431 ns) + CELL(0.738 ns) 4.102 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 4 REG LC_X16_Y7_N1 0 " "Info: 4: + IC(0.431 ns) + CELL(0.738 ns) = 4.102 ns; Loc. = LC_X16_Y7_N1; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "1.169 ns" { sld_hub:sld_hub_inst|HUB_TDO~517 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.620 ns 39.49 % " "Info: Total cell delay = 1.620 ns ( 39.49 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.482 ns 60.51 % " "Info: Total interconnect delay = 2.482 ns ( 60.51 % )" { } { } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.102 ns" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1] sld_hub:sld_hub_inst|HUB_TDO~498 sld_hub:sld_hub_inst|HUB_TDO~517 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.889 ns + Shortest register " "Info: + Shortest clock path from clock altera_internal_jtag~TCKUTAP to destination register is 4.889 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 398 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 398; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.178 ns) + CELL(0.711 ns) 4.889 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 2 REG LC_X16_Y7_N1 0 " "Info: 2: + IC(4.178 ns) + CELL(0.711 ns) = 4.889 ns; Loc. = LC_X16_Y7_N1; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.889 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.54 % " "Info: Total cell delay = 0.711 ns ( 14.54 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.178 ns 85.46 % " "Info: Total interconnect delay = 4.178 ns ( 85.46 % )" { } { } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.889 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 4.889 ns - Longest register " "Info: - Longest clock path from clock altera_internal_jtag~TCKUTAP to source register is 4.889 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 398 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 398; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.178 ns) + CELL(0.711 ns) 4.889 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[1\] 2 REG LC_X16_Y6_N6 7 " "Info: 2: + IC(4.178 ns) + CELL(0.711 ns) = 4.889 ns; Loc. = LC_X16_Y6_N6; Fanout = 7; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[1\]'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.889 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.54 % " "Info: Total cell delay = 0.711 ns ( 14.54 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.178 ns 85.46 % " "Info: Total interconnect delay = 4.178 ns ( 85.46 % )" { } { } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.889 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1] } "NODE_NAME" } } } } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.889 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.889 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } } } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } } } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.102 ns" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1] sld_hub:sld_hub_inst|HUB_TDO~498 sld_hub:sld_hub_inst|HUB_TDO~517 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.889 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.889 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a7~porta_we_reg KEY1 CLK 6.892 ns memory " "Info: tsu for memory DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a7~porta_we_reg (data pin = KEY1, clock pin = CLK) is 6.892 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.729 ns + Longest pin memory " "Info: + Longest pin to memory delay is 9.729 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns KEY1 1 PIN PIN_233 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_233; Fanout = 3; PIN Node = 'KEY1'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "" { KEY1 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.827 ns) + CELL(0.427 ns) 9.729 ns DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a7~porta_we_reg 2 MEM M4K_X17_Y10 0 " "Info: 2: + IC(7.827 ns) + CELL(0.427 ns) = 9.729 ns; Loc. = M4K_X17_Y10; Fanout = 0; MEM Node = 'DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a7~porta_we_reg'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "8.254 ns" { KEY1 DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a7~porta_we_reg } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" 276 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.902 ns 19.55 % " "Info: Total cell delay = 1.902 ns ( 19.55 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.827 ns 80.45 % " "Info: Total interconnect delay = 7.827 ns ( 80.45 % )" { } { } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "9.729 ns" { KEY1 DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a7~porta_we_reg } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" 276 2 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.930 ns - Shortest memory " "Info: - Shortest clock path from clock CLK to destination memory is 2.930 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 317 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 317; CLK Node = 'CLK'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.739 ns) + CELL(0.722 ns) 2.930 ns DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a7~porta_we_reg 2 MEM M4K_X17_Y10 0 " "Info: 2: + IC(0.739 ns) + CELL(0.722 ns) = 2.930 ns; Loc. = M4K_X17_Y10; Fanout = 0; MEM Node = 'DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a7~porta_we_reg'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "1.461 ns" { CLK DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a7~porta_we_reg } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" 276 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 74.78 % " "Info: Total cell delay = 2.191 ns ( 74.78 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.739 ns 25.22 % " "Info: Total interconnect delay = 0.739 ns ( 25.22 % )" { } { } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "2.930 ns" { CLK DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a7~porta_we_reg } "NODE_NAME" } } } } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "9.729 ns" { KEY1 DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a7~porta_we_reg } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "2.930 ns" { CLK DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a7~porta_we_reg } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DOUT\[4\] DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a7~porta_address_reg0 13.546 ns memory " "Info: tco from clock CLK to destination pin DOUT\[4\] through memory DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a7~porta_address_reg0 is 13.546 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.930 ns + Longest memory " "Info: + Longest clock path from clock CLK to source memory is 2.930 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 317 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 317; CLK Node = 'CLK'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.739 ns) + CELL(0.722 ns) 2.930 ns DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a7~porta_address_reg0 2 MEM M4K_X17_Y10 4 " "Info: 2: + IC(0.739 ns) + CELL(0.722 ns) = 2.930 ns; Loc. = M4K_X17_Y10; Fanout = 4; MEM Node = 'DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a7~porta_address_reg0'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "1.461 ns" { CLK DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a7~porta_address_reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" 276 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 74.78 % " "Info: Total cell delay = 2.191 ns ( 74.78 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.739 ns 25.22 % " "Info: Total interconnect delay = 0.739 ns ( 25.22 % )" { } { } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "2.930 ns" { CLK DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a7~porta_address_reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" 276 2 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.966 ns + Longest memory pin " "Info: + Longest memory to pin delay is 9.966 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a7~porta_address_reg0 1 MEM M4K_X17_Y10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y10; Fanout = 4; MEM Node = 'DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|ram_block3a7~porta_address_reg0'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "" { DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a7~porta_address_reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" 276 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|q_a\[2\] 2 MEM M4K_X17_Y10 2 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X17_Y10; Fanout = 2; MEM Node = 'DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|altsyncram_56e2:altsyncram1\|q_a\[2\]'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "4.308 ns" { DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a7~porta_address_reg0 DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[2] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/altsyncram_56e2.tdf" 39 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.534 ns) + CELL(2.124 ns) 9.966 ns DOUT\[4\] 3 PIN PIN_162 0 " "Info: 3: + IC(3.534 ns) + CELL(2.124 ns) = 9.966 ns; Loc. = PIN_162; Fanout = 0; PIN Node = 'DOUT\[4\]'" { } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "5.658 ns" { DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[2] DOUT[4] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" "" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" 7 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.432 ns 64.54 % " "Info: Total cell delay = 6.432 ns ( 64.54 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.534 ns 35.46 % " "Info: Total interconnect delay = 3.534 ns ( 35.46 % )" { } { } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "9.966 ns" { DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a7~porta_address_reg0 DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[2] DOUT[4] } "NODE_NAME" } } } } 0} } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "2.930 ns" { CLK DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a7~porta_address_reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV_cmp.qrpt" Compiler "RESERV" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/RESERV.quartus_db" { Floorplan "" "" "9.966 ns" { DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a7~porta_address_reg0 DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[2] DOUT[4] } "NODE_NAME" } } } } 0}
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