reserv.map.qmsg

采用高速A_D的存储示波器设计 在quartus2 中用的 用vhdl语言写的

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd 6 2 " "Info: Found 6 design units, including 2 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HUB_PACK " "Info: Found design unit 1: HUB_PACK" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "HUB_PACK" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 JTAG_PACK " "Info: Found design unit 2: JTAG_PACK" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "JTAG_PACK" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 63 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_hub-rtl " "Info: Found design unit 3: sld_hub-rtl" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "sld_hub-rtl" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 166 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_jtag_state_machine-rtl " "Info: Found design unit 4: sld_jtag_state_machine-rtl" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "sld_jtag_state_machine-rtl" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1012 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_hub " "Info: Found entity 1: sld_hub" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "sld_hub" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 99 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_jtag_state_machine " "Info: Found entity 2: sld_jtag_state_machine" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "sld_jtag_state_machine" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 997 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus41/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "e:/altera/quartus41/libraries/megafunctions/lpm_decode.tdf" "lpm_decode" "" { Text "e:/altera/quartus41/libraries/megafunctions/lpm_decode.tdf" 67 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_9ie.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_9ie.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_9ie " "Info: Found entity 1: decode_9ie" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/decode_9ie.tdf" "decode_9ie" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/decode_9ie.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_dffex-DFFEX " "Info: Found design unit 1: sld_dffex-DFFEX" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "sld_dffex-DFFEX" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_dffex " "Info: Found entity 1: sld_dffex" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "sld_dffex" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Q1\[0\]~0 10 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: Q1\[0\]~0" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" "" "Q1\[0\]~0" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/RESERV.VHD" 22 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~400 10 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~400" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "ram_rom_addr_reg\[0\]~400" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 394 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_shift_cntr_reg\[0\]~8 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: DPRAM:u1\|altsyncram:altsyncram_component\|altsyncram_d071:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_shift_cntr_reg\[0\]~8" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "ram_rom_data_shift_cntr_reg\[0\]~8" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 537 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "9 " "Info: Ignored 9 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "9 " "Info: Ignored 9 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_pt6.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_pt6.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_pt6 " "Info: Found entity 1: cntr_pt6" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/cntr_pt6.tdf" "cntr_pt6" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/cntr_pt6.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_8b8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_8b8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_8b8 " "Info: Found entity 1: cntr_8b8" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/cntr_8b8.tdf" "cntr_8b8" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/cntr_8b8.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_pd8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_pd8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_pd8 " "Info: Found entity 1: cntr_pd8" {  } { { "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/cntr_pd8.tdf" "cntr_pd8" "" { Text "H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt12_Multi/EXPT12_5_RSV/db/cntr_pd8.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:rsv1\|acq_trigger_in_reg\[8\] data_in GND " "Warning: Reduced register sld_signaltap:rsv1\|acq_trigger_in_reg\[8\] with stuck data_in port to stuck value GND" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd" 512 -1 0 } }  } 0}