rominit.s

基于如何开发MPC860处理器系统的核心业务模块QMC的开发程序

	lis	r5, HIADJ( TBSCR_REFA | TBSCR_REFB)
	addi	r5, r5, LO(TBSCR_REFA | TBSCR_REFB)
	sth	r5, TBSCR(0)(r4)

	/* set PIT status and control init value */

	li	r5, PISCR_PS | PISCR_PITF
	sth	r5, PISCR(0)(r4)

	/* set the SPLL frequency */

	lis	r5, HIADJ( (SPLL_MUL_FACTOR << PLPRCR_MF_SHIFT) | \
								PLPRCR_TEXPS)
	addi	r5, r5, LO((SPLL_MUL_FACTOR << PLPRCR_MF_SHIFT) | \
								PLPRCR_TEXPS)
	stw	r5, PLPRCR(0)(r4)

	/* 
	 * we program the MPTPR with the largest allowed divider 
	 * and the PTA value accordingly. So here we figure out the 
	 * correct value for the PTA field.
	 */

	li	r6, MPTPR_PTP_DIV64 
    lis     r11, HIADJ ((REFRESH_VALUE / 64) << MAMR_PTA_SHIFT)
    addi    r11, r11, LO ((REFRESH_VALUE / 64) << MAMR_PTA_SHIFT)
    cmpwi   r11,0
   	bne     mptprInit

	/* try with the divider by 32 */
/*
	li	r6, MPTPR_PTP_DIV32 
        lis     r11, HIADJ ((REFRESH_VALUE / 32) << MAMR_PTA_SHIFT)
        addi    r11, r11, LO ((REFRESH_VALUE / 32) << MAMR_PTA_SHIFT)
        cmpwi   r11,0
        bne     mptprInit
*/
	/* try with the divider by 16 */
/*
	li	r6, MPTPR_PTP_DIV16 
        lis     r11, HIADJ ((REFRESH_VALUE / 16) << MAMR_PTA_SHIFT)
        addi    r11, r11, LO ((REFRESH_VALUE / 16) << MAMR_PTA_SHIFT)
        cmpwi   r11,0
        bne     mptprInit
*/
	/* try with the divider by 8 */
/*
	li	r6, MPTPR_PTP_DIV8 
        lis     r11, HIADJ ((REFRESH_VALUE / 8) << MAMR_PTA_SHIFT)
        addi    r11, r11, LO ((REFRESH_VALUE / 8) << MAMR_PTA_SHIFT)
        cmpwi   r11,0
        bne     mptprInit
*/
	/* try with the divider by 4 */
/*
	li	r6, MPTPR_PTP_DIV4 
        lis     r11, HIADJ ((REFRESH_VALUE / 4) << MAMR_PTA_SHIFT)
        addi    r11, r11, LO ((REFRESH_VALUE / 4) << MAMR_PTA_SHIFT)
        cmpwi   r11,0
        bne     mptprInit
*/
	/* it has to be the divide by 2 */
/*
	li	r6, MPTPR_PTP_DIV2 
        lis     r11, HIADJ ((REFRESH_VALUE / 2) << MAMR_PTA_SHIFT)
        addi    r11, r11, LO ((REFRESH_VALUE / 2) << MAMR_PTA_SHIFT)
*/
mptprInit:
	/* program the MPTPR */

	sth	r6, MPTPR(0)(r4)
 
     /** initialize MAMR **/

        lis     r6, HIADJ (MAMR_DEFAULT_VALUE)
        addi    r6, r6, LO (MAMR_DEFAULT_VALUE)
        or      r6, r6, r11                      
        stw     r6, MAMR(0)(r4)

	/*
	 * load r6/r7 with the start/end address of the UPM table for an
	 * EDO 60ns Dram.
	 */

	lis	r6, HIADJ( UpmTableEdo60)
	addi	r6, r6, LO(UpmTableEdo60)

	lis	r7, HIADJ( UpmTableEdo60End)
	addi	r7, r7, LO(UpmTableEdo60End)

	/* init UPMA for memory access */

	sub	r5, r7, r6		/* compute table size */
	srawi	r5, r5, 2		/* in integer size */

	/* convert UpmTable to ROM based addressing */

	lis	r7, HIADJ(romInit)	
	addi	r7, r7, LO(romInit)

	lis	r8, HIADJ(ROM_TEXT_ADRS)
	addi	r8, r8, LO(ROM_TEXT_ADRS)

	sub	r6, r6, r7		/* subtract romInit base address */
	add	r6, r6, r8 		/* add in ROM_TEXT_ADRS address */

					/* Command: OP=Write, UPMA, MAD=0 */
	lis	r9, HIADJ (MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS0)
	addi	r9, r9, LO(MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS0)

UpmaWriteLoop:	
	/* write the UPM table in the UPM */

	lwz	r10, 0(r6)		/* get data from table */
	stw	r10, MDR(0)(r4)		/* store the data to MD register */

	stw	r9, MCR(0)(r4)		/* issue command to MCR register */

	addi	r6, r6, 4		/* next entry in the table */
	addi	r9, r9, 1		/* next MAD address */
	cmpw	r9, r5			/* done yet ? */
	blt	UpmaWriteLoop

	/* get the DRAM size, and Map the bank 2(,4 & 5) to the Dram area */
	
	lis	r6, HIADJ(DRAM_SIZE)	/* load r6 with the Dram size */
	addi    r6, r6, LO(DRAM_SIZE)

	lis	r5, HIADJ(DRAM_4MEG_SIMM)
	addi    r5, r5, LO(DRAM_4MEG_SIMM)
	cmpw	r6, r5
	beq	dram4meg

	lis	r5, HIADJ(DRAM_8MEG_SIMM)
	addi    r5, r5, LO(DRAM_8MEG_SIMM)
	cmpw	r6, r5
	beq	dram8meg

	lis	r5, HIADJ(DRAM_12MEG_SIMM)
	addi    r5, r5, LO(DRAM_12MEG_SIMM)
	cmpw	r6, r5

dram12meg:
	/* program BR5 & OR5 */

	lis r5, HIADJ(0xffc00000 | OR_CSNT_SAM)
	addi r5, r5, LO(0xffc00000 | OR_CSNT_SAM)
	stw r5, OR5(0)(r4)

	lis	r5, HIADJ( ((0x00800000 + LOCAL_MEM_LOCAL_ADRS) & \
				BR_BA_MSK) | BR_MS_UPMA | BR_V)
	addi r5, r5, LO(((0x00800000 + LOCAL_MEM_LOCAL_ADRS) & \
				BR_BA_MSK) | BR_MS_UPMA | BR_V)
	stw	r5, BR5(0)(r4)

    
dram8meg:
	/* program BR4 & OR4 */

	lis r5, HIADJ(0xffc00000 | OR_CSNT_SAM)
	addi r5, r5, LO(0xffc00000 | OR_CSNT_SAM)
	stw r5, OR4(0)(r4)
	
	lis	r5, HIADJ( ((0x00400000 + LOCAL_MEM_LOCAL_ADRS) & \
				BR_BA_MSK) | BR_MS_UPMA | BR_V)
	addi r5, r5, LO(((0x00400000 + LOCAL_MEM_LOCAL_ADRS) & \
				BR_BA_MSK) | BR_MS_UPMA | BR_V)
	stw	r5, BR4(0)(r4)

	/* change the Address Multiplexing in MAMR */
 
    lwz     r6, MAMR(0)(r4)
    lis     r9, HIADJ(~MAMR_AMA_MSK)
    addi    r9, r9, LO(~MAMR_AMA_MSK)
    and     r6, r6, r9              /* clear the AMA bits in MAMR */
    lis     r9, HIADJ(MAMR_AMA_TYPE_3)
    addi    r9, r9, LO(MAMR_AMA_TYPE_3)
    or      r6, r6, r9              /* set the AMA bits */
    stw     r6, MAMR(0)(r4)

dram4meg:	
	
	lis r5, HIADJ(0xffc00000 | OR_CSNT_SAM)
	addi r5, r5, LO(0xffc00000 | OR_CSNT_SAM)
	stw	r5, OR2(0)(r4)	/* set OR2 to the previously computed value */

	lis	r5, HIADJ( (LOCAL_MEM_LOCAL_ADRS & BR_BA_MSK) | BR_MS_UPMA | \
			    BR_V)
	addi	r5, r5, LO((LOCAL_MEM_LOCAL_ADRS & BR_BA_MSK) | BR_MS_UPMA | \
			    BR_V)
	stw	r5, BR2(0)(r4)


        /* initialize the stack pointer */
	lis	sp, HIADJ(STACK_ADRS)
	addi	sp, sp, LO(STACK_ADRS)
	

	/* go to C entry point */

	addi	sp, sp, -FRAMEBASESZ		/* get frame stack */

	/* 
	 * calculate C entry point: routine - entry point + ROM base 
	 * routine	= romStart
	 * entry point	= romInit	= R7
	 * ROM base	= ROM_TEXT_ADRS = R8
	 * C entry point: romStart - R7 + R8 
	 */

        lis	r6, HIADJ(romStart)	
        addi	r6, r6, LO(romStart)	/* load R6 with C entry point */

	sub	r6, r6, r7		/* routine - entry point */
	add	r6, r6, r8 		/* + ROM base */

	mtlr	r6			/* move C entry point to LR */
	blr				/* jump to the C entry point */

/* UPM initialization table, EDO, 60ns, 50MHz */

UpmTableEdo60:
# 
# /* DRAM 60ns - single read. (offset 0 in upm RAM) */
        .long	0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04
	.long	0x00f3ec00, 0x37f7ec47
# /* offsets 6-7 not used */
        .long	0xffffffff, 0xffffffff
# /* DRAM 60ns - burst read. (offset 8 in upm RAM) */
        .long	0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c
        .long	0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c
        .long	0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47
# /* offsets 14-17 not used */
        .long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff 
# /* DRAM 60ns - single write. (offset 18 in upm RAM) */
        .long	0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47
# /* offsets 1c-1f not used */
        .long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# /* DRAM 60ns - burst write. (offset 20 in upm RAM) */
        .long	0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c
        .long	0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c
        .long	0x0cafcc00, 0x33bfcc4f
# /* offsets 2a-2f not used */
        .long	0xffffffff, 0xffffffff
        .long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# /* DRAM 60ns - refresh. (offset 30 in upm RAM) */
        .long	0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06
        .long	0xffffcc85, 0xffffcc05
# /* offsets 36-3b not used */
	.long	0xffffffff, 0xffffffff
        .long	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# /* DRAM 60ns - exception. (offset 3c in upm RAM) */
        .long	0x33ffcc07
# /* offset 3d-3f not used */
        .long	0xffffffff, 0xffffffff, 0xffffffff
UpmTableEdo60End: