config.h

基于如何开发MPC860处理器系统的核心业务模块QMC的开发程序

/* ads860/config.h - Motorola 860ads board configuration header */

/* Copyright 1984-1997 Wind River Systems, Inc. */

/*
modification history
--------------------
01a,12/5/2000, 	Change DEFAULT_BOOT_LINE;
		#define EDO_DRAM;
		include the DOS file system;
		redefine SPLL to 50Mhz
		add "#define INCLUDE_NETWORK" 
*/

/*
This file contains the configuration parameters for the
Motorola MPC860ADS board.
*/

#ifndef	INCconfigh
#define	INCconfigh

/* BSP version/revision identification, should be placed
 * before #include "configAll.h"
 */

#define BSP_VER_1_1     1
#define BSP_VER_1_2     1
#define BSP_VERSION     "1.2"
#define BSP_REV         "/4"		/* 0 for the first bsp revision */

#include "configAll.h"
#undef  FADS_860T 

#define DEFAULT_BOOT_LINE \
"cpm(0,0)wangbq:c:/windows/vxWorks h=10.1.5.18 e=10.1.5.252 u=target tn=target"

/* DRAM type on the ADS board */

#define EDO_DRAM			/* to define if the DRAM is EDO */ 

#undef INCLUDE_SDRAM		/* to define in case of SDRAM */

/* Cache and MMU not supported */

#ifdef	EDO_DRAM
#   undef USER_I_CACHE_ENABLE
#   undef USER_D_CACHE_ENABLE
#   undef INCLUDE_CACHE_SUPPORT
#endif	/* EDO_DRAM */

#define USER_I_MMU_ENABLE
#define USER_D_MMU_ENABLE
#define INCLUDE_MMU_BASIC

/* Number of TTY definition */

#undef	NUM_TTY
#define	NUM_TTY		N_SIO_CHANNELS		/* defined in 860sar.h */

/* user defined, hardware debug */
#define DRAM_DEBUG

/* Optional timestamp support */

#undef	INCLUDE_TIMESTAMP

/* optional TrueFFS support */

/*#define INCLUDE_TFFS*/
#undef INCLUDE_TFFS

#ifdef INCLUDE_TFFS
#define INCLUDE_DOSFS		/* dosFs file system */
#define INCLUDE_SHOW_ROUTINES	/* show routines for system facilities*/
#endif /* INCLUDE_DOSFS */

/* clock rates */

#define	SYS_CLK_RATE_MIN	1	/* minimum system clock rate */
#define	SYS_CLK_RATE_MAX	8000	/* maximum system clock rate */
#define	AUX_CLK_RATE_MIN	1	/* minimum auxiliary clock rate */
#define	AUX_CLK_RATE_MAX	8000	/* maximum auxiliary clock rate */

/*
 * Cristal Frequency - This macro defines the input oscillator frequency
 * clocking the PPC860. On the ADS board, the CPU is clocked by a cristal
 * running at 4 Mhz.
 */

#define CRISTAL_FREQ		4000000			/* 4 Mhz */

/*
 * SPLL_FREQ_REQUESTED - This macro defined the expected system PLL (SPLL)
 * frequency divided by 2. The two supported frequencies are either 25
 * or 50 MHz. Use 50Mhz in the case of a FADS860T board.
 */


#define SPLL_FREQ_REQUESTED  FREQ_50_MHZ        /*      25 Mhz => 50Mhz */
/*#define SPLL_FREQ_REQUESTED  FREQ_25_MHZ */            /* 25 Mhz => 50Mhz */

/*
 * DRAM refresh frequency - This macro defines the DRAM refresh frequency.
 * e.i: A DRAM with 1024 rows to refresh in 16ms: 
 * DRAM_REFRESH_FREQ = 1024/ 16E-3 = 64E3 hz
 */

#define DRAM_REFRESH_FREQ	64000	

/*
 * Baud Rate Generator division factor - 0 for division by 1
 *					 1 for division by 4
 *					 2 for division by 16
 *					 3 for division by 64
 */

#define BRGCLK_DIV_FACTOR  0

#define INCLUDE_END              /* Enhanced Network Driver see configNet.h */
#undef INCLUDE_END
#define INCLUDE_NETWORK
#undef INCLUDE_NETWORK
#undef INCLUDE_MOT_FEC          	/* define if you are using the FEC. */
    
#ifdef	INCLUDE_NETWORK
    #define INCLUDE_CPM		/* include the CPM ethernet driver */
#endif /* INCLUDE_NETWORK */

/* remove unnecessary drivers */

#undef INCLUDE_BP
#undef INCLUDE_EX
#undef INCLUDE_ENP
#undef INCLUDE_SM_NET
#undef INCLUDE_SM_SEQ_ADD

/* miscellaneous definitions */
 
#define NV_RAM_SIZE     NONE            /* no NVRAM */
 
/* Memory addresses */

#define LOCAL_MEM_LOCAL_ADRS	0x00000000	/* Base of RAM */
#define LOCAL_MEM_SIZE			0x00400000 	/* 4 Mbyte memory available */

#define DRAM_BASE_ADRS_0		0X00000000
#define DRAM_SIZE_0       		0x00400000
#define DRAM_BASE_ADRS_1 		0X00400000
#define DRAM_SIZE_1       		0x00400000
#define DRAM_BASE_ADRS_2	 	0X00800000
#define DRAM_SIZE_2 	      	0x00400000
/*
#define MT90820_BASE_ADRS 		0x02100000
#define MT90820_SIZE      		0x00008000
*/

#define ROM_BASE_ADRS			0x02800000	/* base address of ROM */
#define ROM_TEXT_ADRS			ROM_BASE_ADRS + 0x100
#define ROM_SIZE				   0x00400000 	

#define AM29F040B_ADRS       	0x02c00000
#define AM29F040B_SIZE          0x00080000	

#define SRAM_BASE_ADRS 			0x03000000
#define SRAM_SIZE       		0x00200000	/* 2M */

#define MT90840_BASE_ADRS       0x03200000
#define MT90840_SIZE            0x00100000  /* 1M */

#define DS2154_ADRS(n)          (0x10000000 + 0x00800000 * n)
#define DS2154_SIZE             0x00800000 /* 64K */

/* RAM address for ROM boot */
#define RAM_HIGH_ADRS			(LOCAL_MEM_LOCAL_ADRS + 0x00200000)

/* RAM address for sys image */
#define RAM_LOW_ADRS			(LOCAL_MEM_LOCAL_ADRS + 0x00010000)

#define USER_RESERVED_MEM		0x00000000	/* user reserved memory size */

/* flash memory support */
#define FLASH_ADRS				0x02800000
#define FLASH_SIZE				0x00400000

/*
 * Default power management mode - selected via vxPowerModeSet() in
 * sysHwInit().
 */

#define DEFAULT_POWER_MGT_MODE  VX_POWER_MODE_DISABLE

#include "860sar.h"				/* include the 860sar params */
#endif	/* INCconfigh */
#if defined(PRJ_BUILD)
#include "prjParams.h"
#endif