project.gfl

xilinx3s400开发板厂家光盘带源码。state状态机、reg

# ProjNav -> New Source -> State Diagram
__projnav/stateCadApp_tcl.rsp
__projnav\stateCadApp.rsp
# Assign Package Pins (Design Module)
if
 $IsCopy 

            Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File"  "$HDLModule"
         
# XST (Creating Lso File) : 
state.lso
# xst flow : RunXST
state_summary.html
# xst flow : RunXST
state.syr
state.prj
state.sprj
state.ana
state.stx
state.cmd_log
state.ngc
state.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\try\examples\statemachine\project/_ngo"
state.ngd
state_ngdbuild.nav
state.bld
state.ucf.untf
state.cmd_log
# Implementation : Map
state_summary.html
# Implementation : Map
state_map.ncd
state.ngm
state.pcf
state.nc1
state.mrp
state_map.mrp
state.mdf
state.cmd_log
MAP_NO_GUIDE_FILE_CPF "state"
state_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
state.twr
state.twx
state.tsi
state.cmd_log
# Implementation : Place & Route
state_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
state.ncd
state.par
state.pad
state_pad.txt
state_pad.csv
state.pad_txt
state.dly
reportgen.log
state.xpi
state.grf
state.itr
state_last_par.ncd
state.placed_ncd_tracker
state.routed_ncd_tracker
state.cmd_log
PAR_NO_GUIDE_FILE_CPF "state"
# XST (Creating Lso File) : 
state.lso
# xst flow : RunXST
state_summary.html
# xst flow : RunXST
state.syr
state.prj
state.sprj
state.ana
state.stx
state.cmd_log
state.ngc
state.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\try\examples\statemachine\project/_ngo"
state.ngd
state_ngdbuild.nav
state.bld
.untf
state.cmd_log
# Implementation : Map
state_summary.html
# Implementation : Map
state_map.ncd
state.ngm
state.pcf
state.nc1
state.mrp
state_map.mrp
state.mdf
state.cmd_log
MAP_NO_GUIDE_FILE_CPF "state"
state_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
state.twr
state.twx
state.tsi
state.cmd_log
# Implementation : Place & Route
state_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
state.ncd
state.par
state.pad
state_pad.txt
state_pad.csv
state.pad_txt
state.dly
reportgen.log
state.xpi
state.grf
state.itr
state_last_par.ncd
state.placed_ncd_tracker
state.routed_ncd_tracker
state.cmd_log
PAR_NO_GUIDE_FILE_CPF "state"
# xst flow : RunXST
state_summary.html
# XST (Creating Lso File) : 
state.lso
# xst flow : RunXST
state_summary.html
# xst flow : RunXST
state.syr
state.prj
state.sprj
state.ana
state.stx
state.cmd_log
state.ngc
state.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\try\examples\statemachine\project/_ngo"
state.ngd
state_ngdbuild.nav
state.bld
.untf
state.cmd_log
# Implementation : Map
state_summary.html
# Implementation : Map
state_map.ncd
state.ngm
state.pcf
state.nc1
state.mrp
state_map.mrp
state.mdf
state.cmd_log
MAP_NO_GUIDE_FILE_CPF "state"
state_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
state.twr
state.twx
state.tsi
state.cmd_log
# Implementation : Place & Route
state_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
state.ncd
state.par
state.pad
state_pad.txt
state_pad.csv
state.pad_txt
state.dly
reportgen.log
state.xpi
state.grf
state.itr
state_last_par.ncd
state.placed_ncd_tracker
state.routed_ncd_tracker
state.cmd_log
PAR_NO_GUIDE_FILE_CPF "state"
# Bencher : Creating project file
tt_bencher.prj
# ProjNav -> New Source -> TBW
tt.vhw
tt.ano
tt.tfw
tt.ant
# Bencher : Creating project file
tt_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
tt_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
tt_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# ISim flow : Creating project file
tt_gen.prj
tt.isim_gen_prj
work
# ISim : Generate Expected Simulation Results
ISIM_FILE_CPF
tt_gen.prj
tt_tbxr.exe
tt.isim_gen_exe
isim
*.auxlib
isim.tmp_save
xilinxsim.ini
# ISim : Generate Expected Simulation Results
ISIM_FILE_CPF
tt_gen.prj
isim.cmd
genExpectedResults.cmd
isim
isim.log
isimwavedata.xwv

isim.hdlsourcefiles
# Bencher : Creating project file
tt_bencher.prj
# ModelSim : Generate Expected Simulation Results
# Bencher : Creating project file
tt_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# xst flow : RunXST
state_summary.html
# Assign Package Pins (Design Module)
if
 $IsCopy 

            Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File"  "$HDLModule"
         
# XST (Creating Lso File) : 
state.lso
# xst flow : RunXST
state_summary.html
# xst flow : RunXST
state.syr
state.prj
state.sprj
state.ana
state.stx
state.cmd_log
state.ngc
state.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\try\3s400changed\s2_state\state_machine2\project/_ngo"
state.ngd
state_ngdbuild.nav
state.bld
state.ucf.untf
state.cmd_log
# XST (Creating Lso File) : 
shell_state.lso
# xst flow : RunXST
shell_state_summary.html
# xst flow : RunXST
shell_state.syr
shell_state.prj
shell_state.sprj
shell_state.ana
shell_state.stx
shell_state.cmd_log
shell_state.ngc
shell_state.ngr
# Assign Package Pins (Design Module)
if
 $IsCopy 

            Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File"  "$HDLModule"
         
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\try\3s400changed\s2_state\state_machine2\project/_ngo"
state.ngd
state_ngdbuild.nav
state.bld
state.ucf.untf
state.cmd_log
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\try\3s400changed\s2_state\state_machine2\project/_ngo"
state.ngd
state_ngdbuild.nav
state.bld
state.ucf.untf
state.cmd_log
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\try\3s400changed\s2_state\state_machine2\project/_ngo"
state.ngd
state_ngdbuild.nav
state.bld
state.ucf.untf
state.cmd_log
# Implementation : Map
state_summary.html
# Implementation : Map
state_map.ncd
state.ngm
state.pcf
state.nc1
state.mrp
state_map.mrp
state.mdf
state.cmd_log
MAP_NO_GUIDE_FILE_CPF "state"
state_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
state.twr
state.twx
state.tsi
state.cmd_log
# Implementation : Place & Route
state_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
state.ncd
state.par
state.pad
state_pad.txt
state_pad.csv
state.pad_txt
state.dly
reportgen.log
state.xpi
state.grf
state.itr
state_last_par.ncd
state.placed_ncd_tracker
state.routed_ncd_tracker
state.cmd_log
PAR_NO_GUIDE_FILE_CPF "state"
# Assign Package Pins (Design Module)
if
 $IsCopy 

            Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File"  "$HDLModule"
         
# XST (Creating Lso File) : 
shell_state.lso
# xst flow : RunXST
shell_state_summary.html
# xst flow : RunXST
shell_state.syr
shell_state.prj
shell_state.sprj
shell_state.ana
shell_state.stx
shell_state.cmd_log
shell_state.ngc
shell_state.ngr
# Assign Package Pins (Design Module)
if
 $IsCopy 

            Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File"  "$HDLModule"
         
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\try\3s400changed\s2_state\state_machine2\project/_ngo"
shell_state.ngd
shell_state_ngdbuild.nav
shell_state.bld
shell_state.ucf.untf
shell_state.cmd_log
# Implementation : Map
shell_state_summary.html
# Implementation : Map
shell_state_map.ncd
shell_state.ngm
shell_state.pcf
shell_state.nc1
shell_state.mrp
shell_state_map.mrp
shell_state.mdf
shell_state.cmd_log
MAP_NO_GUIDE_FILE_CPF "shell_state"
shell_state_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
shell_state.twr
shell_state.twx
shell_state.tsi
shell_state.cmd_log
# Implementation : Place & Route
shell_state_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
shell_state.ncd
shell_state.par
shell_state.pad
shell_state_pad.txt
shell_state_pad.csv
shell_state.pad_txt
shell_state.dly
reportgen.log
shell_state.xpi
shell_state.grf
shell_state.itr
shell_state_last_par.ncd
shell_state.placed_ncd_tracker
shell_state.routed_ncd_tracker
shell_state.cmd_log
PAR_NO_GUIDE_FILE_CPF "shell_state"
# Generate Programming File
__projnav/shell_state_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
shell_state.ut
# Generate Programming File
shell_state.bgn
shell_state.rbt
shell_state.ll
shell_state.msk
shell_state.drc
shell_state.nky
shell_state.bit
shell_state.bin
shell_state.isc
shell_state.cmd_log
# Configure Device (iMPACT)
shell_state.prm
shell_state.isc
shell_state.svf
xilinx.sys
shell_state.mcs
shell_state.exo
shell_state.hex
shell_state.tek