sw_led.gfl

xilinx3s400板厂家光盘的实验源码！led、fre

# XST (Creating Lso File) : 
sw_led.lso
# xst flow : RunXST
sw_led_summary.html
# xst flow : RunXST
sw_led.syr
sw_led.prj
sw_led.sprj
sw_led.ana
sw_led.stx
sw_led.cmd_log
# XST (Creating Lso File) : 
sw_led.lso
# xst flow : RunXST
sw_led_summary.html
# xst flow : RunXST
sw_led.syr
sw_led.prj
sw_led.sprj
sw_led.ana
sw_led.stx
sw_led.cmd_log
# XST (Creating Lso File) : 
sw_led.lso
# xst flow : RunXST
sw_led_summary.html
# xst flow : RunXST
sw_led.syr
sw_led.prj
sw_led.sprj
sw_led.ana
sw_led.stx
sw_led.cmd_log
sw_led.ngc
sw_led.ngr
# xst flow : RunXST
sw_led_summary.html
# xst flow : RunXST
sw_led_summary.html
# xst flow : RunXST
sw_led_summary.html
# Assign Package Pins (Design Module)
if
 $IsCopy 

            Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File"  "$HDLModule"
         
# xst flow : RunXST
sw_led_summary.html
# xst flow : RunXST
sw_led_summary.html
# xst flow : RunXST
sw_led_summary.html
# xst flow : RunXST
sw_led_summary.html
# xst flow : RunXST
sw_led_summary.html
# Assign Package Pins (Design Module)
if
 $IsCopy 

            Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File"  "$HDLModule"
         
# xst flow : RunXST
sw_led_summary.html
# xst flow : RunXST
sw_led_summary.html
# XST (Creating Lso File) : 
sw_led.lso
# xst flow : RunXST
sw_led_summary.html
# xst flow : RunXST
sw_led.syr
sw_led.prj
sw_led.sprj
sw_led.ana
sw_led.stx
sw_led.cmd_log
sw_led.ngc
sw_led.ngr
# XST (Creating Lso File) : 
sw_led.lso
# xst flow : RunXST
sw_led_summary.html
# xst flow : RunXST
sw_led.syr
sw_led.prj
sw_led.sprj
sw_led.ana
sw_led.stx
sw_led.cmd_log
sw_led.ngc
sw_led.ngr
# XST (Creating Lso File) : 
sw_led.lso
# xst flow : RunXST
sw_led_summary.html
# xst flow : RunXST
sw_led.syr
sw_led.prj
sw_led.sprj
sw_led.ana
sw_led.stx
sw_led.cmd_log
sw_led.ngc
sw_led.ngr
# XST (Creating Lso File) : 
sw_led.lso
# xst flow : RunXST
sw_led_summary.html
# xst flow : RunXST
sw_led.syr
sw_led.prj
sw_led.sprj
sw_led.ana
sw_led.stx
sw_led.cmd_log
sw_led.ngc
sw_led.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\xuexi\dz\spartan\board\3s400\examples\examples\s1_sw_led\project/_ngo"
sw_led.ngd
sw_led_ngdbuild.nav
sw_led.bld
sw_led.ucf.untf
sw_led.cmd_log
# Create Timing Constraints
# Assign Package Pins (Design Module)
if
 $IsCopy 

            Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File"  "$HDLModule"
         
# Create Area Constraints
Xilinx::Dpm::dpm_flowUtilsEndScriptMarker
0
# Assign Package Pins (Design Module)
if
 $IsCopy 

            Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File"  "$HDLModule"
         
# xst flow : RunXST
sw_led_summary.html
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"d:\xuexi\dz\spartan\board\3s400\examples\examples\s1_sw_led\project/_ngo"
sw_led.ngd
sw_led_ngdbuild.nav
sw_led.bld
sw_led.ucf.untf
sw_led.cmd_log
# Implementation : Map
sw_led_summary.html
# Implementation : Map
sw_led_map.ncd
sw_led.ngm
sw_led.pcf
sw_led.nc1
sw_led.mrp
sw_led_map.mrp
sw_led.mdf
sw_led.cmd_log
MAP_NO_GUIDE_FILE_CPF "sw_led"
sw_led_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
sw_led.twr
sw_led.twx
sw_led.tsi
sw_led.cmd_log
# Implementation : Place & Route
sw_led_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
sw_led.ncd
sw_led.par
sw_led.pad
sw_led_pad.txt
sw_led_pad.csv
sw_led.pad_txt
sw_led.dly
reportgen.log
sw_led.xpi
sw_led.grf
sw_led.itr
sw_led_last_par.ncd
sw_led.placed_ncd_tracker
sw_led.routed_ncd_tracker
sw_led.cmd_log
PAR_NO_GUIDE_FILE_CPF "sw_led"
# Generate Programming File
__projnav/sw_led_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
sw_led.ut
# Generate Programming File
sw_led.bgn
sw_led.rbt
sw_led.ll
sw_led.msk
sw_led.drc
sw_led.nky
sw_led.bit
sw_led.bin
sw_led.isc
sw_led.cmd_log
# xst flow : RunXST
sw_led_summary.html
# Bencher : Creating project file
test_bencher.prj
# ProjNav -> New Source -> TBW
test.vhw
test.ano
test.tfw
test.ant
# Bencher : Creating project file
test_bencher.prj
# ProjNav -> New Source -> TBW
test.vhw
test.ano
test.tfw
test.ant
# Bencher : Creating project file
test_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
test_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
test_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
test_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# ISim flow : Creating project file
test_stx.prj
test.isim_stx_prj
work
# ISim : Check Syntax
*.auxlib
isim
isim_temp
xilinxsim.ini
test.isim_stx
# ISim flow : Creating project file
test_beh.prj
test.isim_beh_prj
work
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_beh.prj
test_isim_beh.exe
test.isim_beh_exe
isim
*.auxlib
isim.tmp_save
xilinxsim.ini
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_beh.prj
isim.cmd
genExpectedResults.cmd
isim
isim.log
isimwavedata.xwv
test.isim_beh_log
isim.hdlsourcefiles
# xst flow : RunXST
sw_led_summary.html
# Bencher : Creating project file
test_bencher.prj
# ProjNav -> New Source -> TBW
test.vhw
test.ano
test.tfw
test.ant
# Bencher : Creating project file
test_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
test_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
test_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
test_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test.vhw
test.ano
test.tfw
test.ant
# ISim flow : Creating project file
test_gen.prj
test.isim_gen_prj
work
# ISim : Generate Expected Simulation Results
ISIM_FILE_CPF
test_gen.prj
test_tbxr.exe
test.isim_gen_exe
isim
*.auxlib
isim.tmp_save
xilinxsim.ini
# ISim : Generate Expected Simulation Results
ISIM_FILE_CPF
test_gen.prj
isim.cmd
genExpectedResults.cmd
isim
isim.log
isimwavedata.xwv

isim.hdlsourcefiles
# Bencher : Creating project file
test_bencher.prj
# ModelSim : Generate Expected Simulation Results
# ISim : Generate Expected Simulation Results
ISIM_FILE_CPF
test_gen.prj
isim.cmd
genExpectedResults.cmd
isim
isim.log
isimwavedata.xwv

isim.hdlsourcefiles
# Bencher : Creating project file
test_bencher.prj
# ModelSim : Generate Expected Simulation Results
# ISim flow : Creating project file
test_beh.prj
test.isim_beh_prj
work
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_beh.prj
test_isim_beh.exe
test.isim_beh_exe
isim
*.auxlib
isim.tmp_save
xilinxsim.ini
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_beh.prj
isim.cmd
genExpectedResults.cmd
isim
isim.log
isimwavedata.xwv
test.isim_beh_log
isim.hdlsourcefiles
# Implementation : Generate Post-Place & Route Simulation Model
sw_led_timesim.v
sw_led_timesim.nlf
sw_led.versim_par
sw_led.par_nlf
sw_led.cmd_log
sw_led_timesim.v
sw_led_timesim.sdf
sw_led_timesim.sdf
# Bencher : Creating project file
test_bencher.prj
# Hidden Remap : Simulate Post-Place & Route Verilog Model
test.timesim_tfw
_remap.tmp
# ISim flow : Creating project file
test_par.prj
test.isim_par_prj
work
# ISim : Simulate Post-Place & Route HDL Model
ISIM_FILE_CPF
test_par.prj
test_isim_par.exe
test.isim_par_exe
isim
*.auxlib
isim.tmp_save
xilinxsim.ini
# ISim : Simulate Post-Place & Route HDL Model
ISIM_FILE_CPF
test_par.prj
isim.cmd
genExpectedResults.cmd
isim
isim.log
isimwavedata.xwv
test.isim_par_log
isim.hdlsourcefiles
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_beh.prj
isim.cmd
genExpectedResults.cmd
isim
isim.log
isimwavedata.xwv
test.isim_beh_log
isim.hdlsourcefiles
# ISim : Simulate Post-Place & Route HDL Model
ISIM_FILE_CPF
test_par.prj
isim.cmd
genExpectedResults.cmd
isim
isim.log
isimwavedata.xwv
test.isim_par_log
isim.hdlsourcefiles
# ISim flow : Creating project file
test_stx.prj
test.isim_stx_prj
work
# ISim : Check Syntax
*.auxlib
isim
isim_temp
xilinxsim.ini
test.isim_stx
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_beh.prj
isim.cmd
genExpectedResults.cmd
isim
isim.log