📄 hdlc.h
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/***********************************************************************/
/* */
/* MODULE: BDTest/hdlc.h */
/* DATE: 99/06/05 */
/* PURPOSE: hdlc(high level data link control) header */
/* */
/*---------------------------------------------------------------------*/
/* Copyright (C) 1997 Samsung Electronics. */
/* */
/* programmed by hbahn */
/***********************************************************************/
#ifndef _HDLC_H
#define _HDLC_H
#define HDLC_STATION_ADDR 0x012345678
#define HDLC_BAUDRATE 64000
#define HDLC_PREAMBLE 0xAA
#define HDLCA 0
#define HDLCB 1
#define MODE_DMA 0
#define MODE_INTERRUPT 1
#define HDLCPORTNUM 2
#define MaxTxBufferDescriptor 3
#define MaxRxBufferDescriptor 16
#define HDLC_MTU 1500
#define NonCache 0x4000000
#define BOwnership_CPU 0x7fffffff
#define BOwnership_DMA 0x80000000
// Macro function for define HDLC Registers
#define HCON0(channel) (VPint(Base_Addr+0x7000 + channel*0x1000))
#define HCON1(channel) (VPint(Base_Addr+0x7004 + channel*0x1000))
#define HSTAT(channel) (VPint(Base_Addr+0x7008 + channel*0x1000))
#define HINTEN(channel) (VPint(Base_Addr+0x700c + channel*0x1000))
#define HTXFIFOC(channel) (VPint(Base_Addr+0x7010 + channel*0x1000))
#define HTXFIFOT(channel) (VPint(Base_Addr+0x7014 + channel*0x1000))
#define HRXFIFO(channel) (VPint(Base_Addr+0x7018 + channel*0x1000))
#define HSADR(channel) (VPint(Base_Addr+0x701c + channel*0x1000))
#define HBRGTC(channel) (VPint(Base_Addr+0x7020 + channel*0x1000))
#define HPRMB(channel) (VPint(Base_Addr+0x7024 + channel*0x1000))
#define HDMATXMA(channel) (VPint(Base_Addr+0x7028 + channel*0x1000))
#define HDMARXMA(channel) (VPint(Base_Addr+0x702c + channel*0x1000))
#define HDMATXCNT(channel) (VPint(Base_Addr+0x7030 + channel*0x1000))
#define HDMARXCNT(channel) (VPint(Base_Addr+0x7034 + channel*0x1000))
#define HDMARXBCNT(channel) (VPint(Base_Addr+0x7038 + channel*0x1000))
// Macro function for HDLC controller control
#define HDLC_Tx_Enable(channel) HCON0(channel) |= TxEN
#define HDLC_Rx_Enable(channel) HCON0(channel) |= RxEN
#define HDMA_Tx_Enable(channel) HCON0(channel) |= DTxEN
#define HDMA_Rx_Enable(channel) HCON0(channel) |= DRxEN
#define HDLC_Loopback_enable(channel) HCON1(channel) |= TxLOOP
#define HDLC_Loopback_disable(channel) HCON1(channel) &= ~TxLOOP
// HDLC Control Register 0 (HCON0)
#define TxRS 0x00000001 // bit 0
#define RxRS 0x00000002 // bit 1
#define DTxRS 0x00000004 // bit 2
#define DRxRS 0x00000008 // bit 3
#define BRGEN 0x00000020 // bit 5
#define DPLLEN 0x00000040 // bit 6
#define TxEN 0x00000100 // bit 8
#define RxEN 0x00000200 // bit 9
#define DTxEN 0x00000400 // bit 10
#define DRxEN 0x00000800 // bit 11
#define TxWA 0x00003000 // bit 12:13
#define TxWA_MASK 0xFFFFCFFF // bit 12:13
#define TxWA1 0x00001000 // bit 12:13
#define TxWA2 0x00002000 // bit 12:13
#define TxWA3 0x00003000 // bit 12:13
#define RxWA 0x0000C000 // bit 14:15
#define RxWA_MASK 0xFFFF3FFF // bit 14:15
#define RxWA1 0x00004000 // bit 14:15
#define RxWA2 0x00008000 // bit 14:15
#define RxWA3 0x0000C000 // bit 14:15
#define TxSTCL 0x00010000 // bit 16
#define RxSTCL 0x00020000 // bit 17
#define DPLLTMCL 0x00040000 // bit 18
#define DPLLOMCL 0x00080000 // bit 19
#define TxCPOS 0x00100000 // bit 20
#define TxCNEG 0x00000000 // bit 20
#define RxCPOS 0x00200000 // bit 21
#define RxCNEG 0x00000000 // bit 21
#define TxABT 0x01000000 // bit 24
#define TxRTS 0x02000000 // bit 25
#define TxDTR 0x04000000 // bit 26
#define RxDISCON 0x08000000 // bit 27
#define TxNOCRC 0x10000000 // bit 28
#define RxNOCRC 0x20000000 // bit 29
// HDLC Control Register 1 (HCON1)
#define F4WM 0x00000001 // bit 0
#define TxLittle 0x00000002 // bit 1
#define RxLittle 0x00000004 // bit 2
#define DTxMADEC 0x00000008 // bit 3
#define DRxMADEC 0x00000010 // bit 4
#define DTxMAINC 0x00000000 // bit 3
#define DRxMAINC 0x00000000 // bit 4
#define DRxSTOPTC 0x00000020 // bit 5
#define TxFLAGIDLE 0x00000040 // bit 6
#define TxPREAMBLE 0x00000080 // bit 7
#define TxSDFL 0x00000100 // bit 8
#define TxABTEXT 0x00000200 // bit 9
#define TxLOOP 0x00000400 // bit 10
#define RxASEN 0x00000800 // bit 11
#define RxAEXT 0x00001000 // bit 12
#define RxECHO 0x00002000 // bit 13
#define RxFDSEN 0x00004000 // bit 14
#define DF 0x00070000 // bit 16:17:18
#define DF_MASK 0xFFF8FFFF // bit 16:17:18
#define DF_NRZ 0x00000000 // bit 16:17:18
#define DF_NRZI 0x00010000 // bit 16:17:18
#define DF_FM0 0x00020000 // bit 16:17:18
#define DF_FM1 0x00030000 // bit 16:17:18
#define DF_Manchester 0x00040000 // bit 16:17:18
#define BRGCLK_MASK 0xFFFEFFFF
#define BRGCLK_MCLK 0x00080000 // bit 19
#define BRGCLK_RXC 0x00000000
#define DPLLCLK 0x00700000 // bit 20:21:22
#define DPLLCLK_MASK 0xFF8FFFFF // bit 20:21:22
#define DPLLCLK_TXC 0x00000000 // bit 20:21:22
#define DPLLCLK_RXC 0x00100000 // bit 20:21:22
#define DPLLCLK_MCLK 0x00200000 // bit 20:21:22
#define DPLLCLK_BRG1 0x00300000 // bit 20:21:22
#define DPLLCLK_BRG2 0x00400000 // bit 20:21:22
#define DPLLCLK_BRG3 0x00500000 // bit 20:21:22
#define TxCLK 0x03800000 // bit 23:24:25
#define TxCLK_MASK 0xFC7FFFFF // bit 23:24:25
#define TxCLK_TXC 0x00000000 // bit 23:24:25
#define TxCLK_RXC 0x00800000 // bit 23:24:25
#define TxCLK_DPLL 0x01000000 // bit 23:24:25
#define TxCLK_BRG1 0x01800000 // bit 23:24:25
#define TxCLK_BRG2 0x02000000 // bit 23:24:25
#define TxCLK_BRG3 0x02800000 // bit 23:24:25
#define RxCLK 0x1C000000 // bit 26:27:28
#define RxCLK_MASK 0xE3FFFFFF // bit 26:27:28
#define RxCLK_TXC 0x00000000 // bit 26:27:28
#define RxCLK_RXC 0x04000000 // bit 26:27:28
#define RxCLK_DPLL 0x08000000 // bit 26:27:28
#define RxCLK_BRG1 0x0C000000 // bit 26:27:28
#define RxCLK_BRG2 0x10000000 // bit 26:27:28
#define RxCLK_BRG3 0x14000000 // bit 26:27:28
#define TxOCLK_TXC 0x00000000 // bit 31:30:29
#define TxOCLK_RXC 0x20000000 // bit 31:30:29
#define TxOCLK_BRG1 0x40000000 // bit 31:30:29
#define TxOCLK_BRG2 0x60000000 // bit 31:30:29
#define TxOCLK_BRG3 0x80000000 // bit 31:30:29
// HDLC Status Register (HSTAT)
#define RxRB 0x0000000F // bit3 - bit0
#define TxFC 0x00000100 // bit8
#define TxFA 0x00000200 // bit9
#define TxCTS 0x00000400 // bit10
#define TxSCTS 0x00000800 // bit11
#define TxU 0x00001000 // bit12
#define RxFA 0x00002000 // bit13
#define RxFAP 0x00004000 // bit14
#define RxFD 0x00008000 // bit15
#define RxDCD 0x00010000 // bit16
#define RxSDCD 0x00020000 // bit17
#define RxAERR 0x00040000 // bit18
#define RxFV 0x00080000 // bit19
#define RxIDLE 0x00100000 // bit20
#define RxABT 0x00200000 // bit21
#define RxFERR 0x00400000 // bit22
#define RxOV 0x00800000 // bit23
#define DTxSTOP 0x01000000 // bit24
#define DTxABT 0x02000000 // bit25
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