hdlcinit.c

s3c4510的开发板snds100的源代码。

						(U32)CTxBDPtr->NextBufferDescriptor ;

					// Step 5. Clear owner to CPU
					CTxBDPtr->BufferDataPtr &= BOwnership_CPU ; 
				}
		}

	}


	// 8. HDLC Transmit Status
	if ( IntHdlcStatus & ( TxFC | TxU | TxCTS | TxSCTS ) )
	{
		if ( IntHdlcStatus & TxFC ) {
			gHdlcTxStatus[channel].TxFrameComplete++ ;
			HSTAT(channel) |= TxFC ;
		}

		if ( IntHdlcStatus & TxU ) {
			gHdlcTxStatus[channel].TxUnderrun++ ;
			HSTAT(channel) |= TxU ;
		}

		if (IntHdlcStatus & TxCTS)
			gHdlcTxStatus[channel].TxLevelOfCTS++ ;

		if (IntHdlcStatus & TxSCTS) {
			gHdlcTxStatus[channel].TxTransitionOfCTS++ ;
			}
	}


	// H9. DLC DPLL Error
	if ( IntHdlcStatus & ( DPLLOM | DPLLTM ) ) {
		if ( IntHdlcStatus & DPLLOM ) {
			gHdlcDPLLStatus[channel].DPLLOneClkMiss++ ;
			HSTAT(channel) |= DPLLOM ;
		}

		if ( IntHdlcStatus & DPLLTM ) {
			gHdlcDPLLStatus[channel].DPLLTwoClkMiss++ ;
			HSTAT(channel) |= DPLLTM ;
		}
	}

}

/*
 *  Function : HDLCB_Isr
 *  Description : HDLC Interrupt service routine for channel B
 */
void HDLCB_isr(void)
{
	sBufferDescriptor 	*CRxBDPtr, *CTxBDPtr ;
	HDLC_Device_Entry  	*Dev ;
	U32			RxLength, TxLength ;
	U32			channel = HDLCB ;
	U32 			IntHdlcStatus ;

	// 1. Get device entry pointer
	Dev = (HDLC_Device_Entry *)&HDLC_Dev[channel] ; 

	// 2. Save current HDLC status
	IntHdlcStatus = HSTAT(channel) ;

	// 3. Process HDMA receive operation
	//    This routine is used when HDLC DMA mode receive operation
	if ( IntHdlcStatus & ( DRxSTOP | DRxABT) ) {

		if ( IntHdlcStatus & DRxSTOP ) {
			gHdlcRxStatus[channel].DMARxStop++ ;
			HSTAT(channel) |= DRxSTOP ;
		}
		else if ( IntHdlcStatus & DRxABT ) {
			gHdlcRxStatus[channel].DMARxABT++ ;
			HSTAT(channel) |= DRxABT ;
		}

		// Step 1. Get current receive buffer descriptor point
		CRxBDPtr = (sBufferDescriptor *)gCRxBDPtr[channel];

		// Step 2. Clear owner to CPU
		CRxBDPtr->BufferDataPtr &= BOwnership_CPU ; 

		// Step 3. Get length and status
		CRxBDPtr->LengthField = RxLength = HDMARXBCNT(channel) ;
		CRxBDPtr->StatusField = IntHdlcStatus ; 

		// Step 4. Get Next buffer descriptor
		gCRxBDPtr[channel] = (U32)CRxBDPtr->NextBufferDescriptor ;

		// Step 5. Initialize HDLC DMA for receive
		HDLC_Rx_init(channel) ;
	}


	// 4. Process HDLC receive operation
	//    This routine is used when HDLC interrupt mode receive operation
	if (Dev->HDLC_Rx_Mode == MODE_INTERRUPT) {
		if (IntHdlcStatus & (RxFA | RxFV | RxFERR) ) {
			if (IntHdlcStatus & RxFA) 
				gHdlcRxStatus[channel].RxFIFOAvalable++ ;
	
			if (IntHdlcStatus & (RxFV | RxFERR) ) {
		
				if (IntHdlcStatus & RxFV) 
					gHdlcRxStatus[channel].RxLastFrameValid++ ;
		
				if ( IntHdlcStatus & RxFERR ) 
					gHdlcRxStatus[channel].RxFrameError++ ;
		
				// Step 1. Read received data from HDLC receive FIFO entry
				ReadDataFromFifo(channel,(HSTAT(channel)&0xF)) ;
		
				// Step 2. Get current receive buffer descriptor point
				CRxBDPtr = (sBufferDescriptor *)gCRxBDPtr[channel];
		
				// Step 3. Clear owner to CPU
				CRxBDPtr->BufferDataPtr &= BOwnership_CPU ; 

				// Step 4. Get length and status
				CRxBDPtr->LengthField = RxLength = 
						ModeInt_RxDataSize[channel] ; 
				CRxBDPtr->StatusField = IntHdlcStatus ; 

				// Step 5. Get Next buffer descriptor
				gCRxBDPtr[channel] = (U32)CRxBDPtr->NextBufferDescriptor ;
		
				// Step 6. Initialize HDLC DMA for receive
				HDLC_Rx_init(channel) ;
			} else
				// Read received data from HDLC receive FIFO entry
				ReadDataFromFifo(channel, 15) ;
		}
	}
	
	// 5. Save HDLC receive status 
	if ( IntHdlcStatus & ( RxOV|RxABT|RxAERR|RxFAP|RxFD|RxDCD|RxSDCD|RxIDLE) ) {

		// HDLC Rx OverRun Error
		if ( IntHdlcStatus & RxOV ) {
			gHdlcRxStatus[channel].RxOverrun++ ;
			HSTAT(channel) |= RxOV ;

			// check all descriptor is used, then enable HDMA Rx
			if ( gCRxBDPtr[channel] == pCRxBDPtr[channel] )
				HDLC_Rx_init(channel) ;
		}
	
		if ( IntHdlcStatus & RxABT ) {
			gHdlcRxStatus[channel].RxAbort++ ;
			HSTAT(channel) |= RxABT ;
			HDLC_Rx_init(channel) ;
		}

		if ( IntHdlcStatus & RxAERR ) 
			gHdlcRxStatus[channel].RxAddressError++ ;

		if (IntHdlcStatus & RxFAP) {
			gHdlcRxStatus[channel].RxFIFOAddrPresent++ ;
			HSTAT(channel) |= RxFAP ;
			}
		if (IntHdlcStatus & RxFD) {
			gHdlcRxStatus[channel].RxFlagDetected++ ;
			HSTAT(channel) |= RxFD ;
			}
		if (IntHdlcStatus & RxDCD) 
			gHdlcRxStatus[channel].RxLevelOfDCD++ ;

		if (IntHdlcStatus & RxSDCD) {
			gHdlcRxStatus[channel].RxTransitionOfDCD++ ;
			HSTAT(channel) |= RxSDCD ;
			}
		if (IntHdlcStatus & RxIDLE) {
			gHdlcRxStatus[channel].RxIdle++ ;
			HSTAT(channel) |= RxIDLE ;
			}
	}

	// 6. HDLC Transmit DMA mode Complete
	if ( IntHdlcStatus & (DTxSTOP | DTxABT) ) {

		if ( IntHdlcStatus & DTxSTOP ) {
			gHdlcTxStatus[channel].DMATxStop++ ;
			HSTAT(channel) |= DTxSTOP ;
		}

		if ( IntHdlcStatus & DTxABT ) {
			gHdlcTxStatus[channel].DMATxABT++ ;
			HSTAT(channel) |= DTxABT ;
		}

		do {
			// Step 1. Get current transmit buffer descriptor pointer 
			//         and length
			CTxBDPtr = (sBufferDescriptor *)gCTxBDPtr[channel];
			TxLength = CTxBDPtr->LengthField ;
	
			// Step 2. Clear Length and Status field
			CTxBDPtr->LengthField = (U32)0x0;
			CTxBDPtr->StatusField = (U32)0x0;
	
			// Step 3. Change ownership to CPU
			CTxBDPtr->BufferDataPtr &= BOwnership_CPU ; 

			// Step 4. Get Next buffer descriptor
			gCTxBDPtr[channel] = (U32)CTxBDPtr->NextBufferDescriptor ;
	

		} while (pCTxBDPtr[channel] == gCTxBDPtr[channel]) ;
	}

	// 7. HDLC Transmit Interrupt mode
	if (Dev->HDLC_Tx_Mode == MODE_INTERRUPT) {
		if  (IntHdlcStatus & TxFA) {
			gHdlcTxStatus[channel].TxFIFOAvailable++ ;

			if ( ModeInt_TxDataSize[channel] > 0)
				// Step 1. write 4 word frame data to FIFO
				if ( !WriteDataToFifo(channel) ) {

					// Step 2. Get current receive buffer descriptor point
					CTxBDPtr = (sBufferDescriptor *)gCTxBDPtr[channel];
					TxLength = CTxBDPtr->LengthField ;
			
					// Step 3. Clear length and status field
					CTxBDPtr->LengthField = (U32)0x0;
					CTxBDPtr->StatusField = (U32)0x0;
			
					// Step 4. Change ownership to CPU
					CTxBDPtr->BufferDataPtr &= BOwnership_CPU ; 

					// Step 5. Get Next buffer descriptor
					gCTxBDPtr[channel] = 
						(U32)CTxBDPtr->NextBufferDescriptor ;

				}
		}

	}


	// 8. HDLC Transmit Status
	if ( IntHdlcStatus & ( TxFC | TxU | TxCTS | TxSCTS ) )
	{
		if ( IntHdlcStatus & TxFC ) {
			gHdlcTxStatus[channel].TxFrameComplete++ ;
			HSTAT(channel) |= TxFC ;
		}

		if ( IntHdlcStatus & TxU ) {
			gHdlcTxStatus[channel].TxUnderrun++ ;
			HSTAT(channel) |= TxU ;
		}

		if (IntHdlcStatus & TxCTS) 
			gHdlcTxStatus[channel].TxLevelOfCTS++ ;

		if (IntHdlcStatus & TxSCTS) {
			gHdlcTxStatus[channel].TxTransitionOfCTS++ ;
			}
	}


	// H9. DLC DPLL Error
	if ( IntHdlcStatus & ( DPLLOM | DPLLTM ) ) {
		if ( IntHdlcStatus & DPLLOM ) {
			gHdlcDPLLStatus[channel].DPLLOneClkMiss++ ;
			HSTAT(channel) |= DPLLOM ;
		}

		if ( IntHdlcStatus & DPLLTM ) {
			gHdlcDPLLStatus[channel].DPLLTwoClkMiss++ ;
			HSTAT(channel) |= DPLLTM ;
		}
	}
}

/*
 *  Function : ReceiveHdlcFrame
 *  Description : Receive HDLC frame
 */
int ReceiveHdlcFrame(U32 channel)
{
	sBufferDescriptor 	*pRxBDPtr ;
	U32			CRxBDPtr ;
	U32			*DataBuffer ;
	U32			Length ;
	U32			Status ;

	// Step 1. Get current frame buffer pointer
	CRxBDPtr = (U32)gCRxBDPtr[channel] ;

	do {
		// Step 2. Get frame buffer pointer for process
		pRxBDPtr = (sBufferDescriptor *)pCRxBDPtr[channel] ;

		// Step 3. Check Ownership is CPU or not
		if ( !((U32)(pRxBDPtr->BufferDataPtr) & BOwnership_DMA) )  {

			// Step 4. If ownership is CPU, then receive frame is exist
			//         So, get this frame to process
			DataBuffer = (U32 *)pRxBDPtr->BufferDataPtr ;
			Length = pRxBDPtr->LengthField  ;
			Status = pRxBDPtr->StatusField  ;

			if ( !( Status & (RxFERR | DRxABT) ) ) {
				// debug message
				Print("\r++> Rx=>BDP:%x, BD:%x, L:%d ", \
					pRxBDPtr, DataBuffer, Length ) ;

#if 0
             			memcpy ((U8 *)&TempBuf,(U8 *)DataBuffer,Length);
#endif
			}
		}
		else break ;

		// Step 5. Change owner to DMA
		(pRxBDPtr->BufferDataPtr) |= BOwnership_DMA;
		pRxBDPtr->LengthField = (U32)0x0;
		pRxBDPtr->StatusField = (U32)0x0;

		// Step 6. check all descriptor is used, then enable HDLC receive
		if ( gCRxBDPtr[channel] == pCRxBDPtr[channel] )
			HDLC_Rx_init(channel) ;

		// Step 7. Get Next Frame Descriptor pointer to process
		pCRxBDPtr[channel] = (U32)(pRxBDPtr->NextBufferDescriptor) ;

	} while (CRxBDPtr != pCRxBDPtr[channel]);

	return 1 ;
}

/*
 *  Function : ToggleLED
 *  Description : Toggle LED flash
 */
void ToggleLED(U32 bit)
{
	U32 reg_value ;

}