c6713regs.h

flash在线烧写

/*******************************************************************************
* FILENAME
*   c6713regs.h
*
* DESCRIPTION
*   Registers Header File
*
*******************************************************************************/

/* Register definitions for C6713 chip  */

/* Define EMIF Registers  */
#define EMIF_GCTL 		0x1800000	/* Address of EMIF global control		*/
#define EMIF_CE0		0x1800008	/* Address of EMIF CE0 control			*/
#define EMIF_CE1		0x1800004	/* Address of EMIF CE1 control			*/
#define EMIF_CE2		0x1800010	/* Address of EMIF CE2 control          */
#define EMIF_CE3		0x1800014	/* Address of EMIF CE3 control          */
#define EMIF_SDCTL		0x1800018	/* Address of EMIF SDRAM control		*/
#define EMIF_SDTIM		0x180001c	/* Address of EMIF SDRAM refresh control*/
#define EMIF_SDEXT		0x1800020	/* Address of EMIF SDRAM extension		*/
 
/* Define McBSP0 Registers */
#define McBSP0_DRR      0x18c0000   /* Address of data receive reg. R       */
#define McBSP0_DXR      0x18c0004   /* Address of data transmit reg.        */
#define McBSP0_SPCR     0x18c0008   /* Address of serial port contl reg.    */
#define McBSP0_RCR      0x18c000C   /* Address of receive control reg.      */
#define McBSP0_XCR      0x18c0010   /* Address of transmit control reg.     */
#define McBSP0_SRGR     0x18c0014   /* Address of sample rate generator reg.*/
#define McBSP0_MCR      0x18c0018   /* Address of multichannel reg.         */
#define McBSP0_RCER     0x18c001C   /* Address of receive channel enable.   */
#define McBSP0_XCER     0x18c0020   /* Address of transmit channel enable.  */
#define McBSP0_PCR      0x18c0024   /* Address of pin control reg.          */

/* Define McBSP1 Registers */
#define McBSP1_DRR      0x1900000   /* Address of data receive reg.         */
#define McBSP1_DXR      0x1900004   /* Address of data transmit reg.        */
#define McBSP1_SPCR     0x1900008   /* Address of serial port contl. reg.   */
#define McBSP1_RCR      0x190000C   /* Address of receive control reg.      */
#define McBSP1_XCR      0x1900010   /* Address of transmit control reg.     */
#define McBSP1_SRGR     0x1900014   /* Address of sample rate generator     */
#define McBSP1_MCR      0x1900018   /* Address of multichannel reg.         */
#define McBSP1_RCER     0x190001C   /* Address of receive channel enable.   */
#define McBSP1_XCER     0x1900020   /* Address of transmit channel enable.  */
#define McBSP1_PCR      0x1900024   /* Address of pin control reg.          */

/* Define L2 Cache Registers */
#define L2CFG           0x1840000   /* Address of L2 config reg             */
#define MAR0            0x1848200   /* Address of mem attribute reg         */

/* Define Interrupt Registers */
#define IMH             0x19c0000   /* Address of Interrupt Multiplexer High*/
#define IML             0x19c0004   /* Address of Interrupt Multiplexer Low */
#define EXTPOL          0x19C0008   /* Address of External interrupt polarity*/
/*Define Device Registers*/
#define DEVCFG          0x19C0200   /* Address of Device Configuration      */
/* Define Timer0 Registers */
#define TIMER0_CTL      0x1940000	/* Address of timer0 control reg.       */
#define TIMER0_PRD      0x1940004	/* Address of timer0 period  reg.       */
#define TIMER0_CNT      0x1940008	/* Address of timer0 counter reg.       */

/* Define Timer1 Registers */
#define TIMER1_CTL      0x1980000	/* Address of timer1 control reg.       */
#define TIMER1_PRD      0x1980004	/* Address of timer1 period reg.        */
#define TIMER1_CNT      0x1980008	/* Address of timer1 counter reg.       */

/* Define EDMA Registers */
#define EDMA_PQSR		0x01A0FFE0	/* Address of priority queue status     */
#define EDMA_CIPR	    0x01A0FFE4	/* Address of channel interrupt pending */
#define EDMA_CIER		0x01A0FFE8	/* Address of channel interrupt enable  */
#define EDMA_CCER		0x01A0FFEC	/* Address of channel chain enable      */
#define EDMA_ER		    0x01A0FFF0	/* Address of event register            */
#define EDMA_EER		0x01A0FFF4	/* Address of event enable register     */
#define EDMA_ECR		0x01A0FFF8	/* Address of event clear register      */
#define EDMA_ESR		0x01A0FFFC	/* Address of event set register        */

/* Define EDMA Transfer Parameter Entry Fields 4 bytes/word */
#define OPT				0*4			/* Options Parameter                    */
#define SRC				1*4			/* SRC Address Parameter                */
#define CNT				2*4			/* Count Parameter                      */
#define DST				3*4			/* DST Address Parameter                */
#define IDX				4*4			/* IDX Parameter                        */
#define LNK				5*4			/* LNK Parameter                        */
						
/* Define EDMA Parameter RAM Addresses */ 
#define EVENT0_PARAMS 0x01A00000
#define EVENT1_PARAMS EVENT0_PARAMS + 0x18
#define EVENT2_PARAMS EVENT1_PARAMS + 0x18
#define EVENT3_PARAMS EVENT2_PARAMS + 0x18
#define EVENT4_PARAMS EVENT3_PARAMS + 0x18
#define EVENT5_PARAMS EVENT4_PARAMS + 0x18
#define EVENT6_PARAMS EVENT5_PARAMS + 0x18
#define EVENT7_PARAMS EVENT6_PARAMS + 0x18
#define EVENT8_PARAMS EVENT7_PARAMS + 0x18
#define EVENT9_PARAMS EVENT8_PARAMS + 0x18
#define EVENTA_PARAMS EVENT9_PARAMS + 0x18
#define EVENTB_PARAMS EVENTA_PARAMS + 0x18
#define EVENTC_PARAMS EVENTB_PARAMS + 0x18
#define EVENTD_PARAMS EVENTC_PARAMS + 0x18
#define EVENTE_PARAMS EVENTD_PARAMS + 0x18
#define EVENTF_PARAMS EVENTE_PARAMS + 0x18
#define EVENTN_PARAMS EVENTF_PARAMS + 0x18
#define EVENTO_PARAMS EVENTN_PARAMS + 0x18

/* Define QDMA Memory Mapped Registers */
#define QDMA_OPT		0x02000000	/* Address of QDMA options parameter register   */
#define QDMA_SRC		0x02000004	/* Address of QDMA Source address register      */
#define QDMA_CNT		0x02000008	/* Address of QDMA counts register              */
#define QDMA_DST		0x0200000C	/* Address of QDMA Destination address register */
#define QDMA_IDX		0x02000010	/* Address of QDMA index register               */
 
/* Define QDMA Pseudo Registers */
#define QDMA_S_OPT		0x02000020	/* Address of QDMA pseudo options register              */
#define QDMA_S_SRC		0x02000024	/* Address of QDMA pseudo Source address register       */
#define QDMA_S_CNT		0x02000028	/* Address of QDMA pseudo frame counts register         */
#define QDMA_S_DST		0x0200002C	/* Address of QDMA pseudo destiination address register */
#define QDMA_S_IDX		0x02000030	/* Address of QDMA pseudo index register                */

/* Define PLL Controller Registers*/
#define PLLCSR          0x01B7C100  /* PLL control/status register    */
#define PLLM            0x01B7C110  /* PLL multiplier control register*/
#define PLLDIV0         0x01B7C114  /* PLL controler divider0 register*/
#define PLLDIV1         0x01B7C118  /* PLL controler divider1 register*/
#define PLLDIV2         0x01B7C11C  /* PLL controler divider2 register*/
#define PLLDIV3         0x01B7C120  /* PLL controler divider3 register*/
#define OSCDIV1         0x01B7C124  /* PLL Oscilllator divider1 register*/

/* Define I2C0 Registers Registers*/
#define I2C0_OAR        0x01B40000  /* I2C0 own address register            */
#define I2C0_IER        0x01B40004  /* I2C0 interrupt enable register       */
#define I2C0_STR        0x01B40008  /* I2C0 interrupt status register       */
#define I2C0_CLKL       0x01B4000C  /* I2C0 clock low-time divider register */
#define I2C0_CLKH       0x01B40010  /* I2C0 clock high-time divider register*/
#define I2C0_CNT        0x01B40014  /* I2C0 data count register             */
#define I2C0_DRR        0x01B40018  /* I2C0 data receive register           */
#define I2C0_SAR        0x01B4001C  /* I2C0 slave address register          */
#define I2C0_DXR        0x01B40020  /* I2C0 data transmit register          */
#define I2C0_MDR        0x01B40024  /* I2C0 mode register                   */
#define I2C0_ISRC       0x01B40028  /* I2C0 interrupt source register       */
#define I2C0_PSC        0x01B40030  /* I2C0 prescaler register              */ 

/* Define GPIO Registers*/
#define GPEN            0x01B00000   /* GPIO enable register             */
#define GPDIR           0x01B00004   /* GPIO direction register          */
#define GPVAL           0x01B00008   /* GPIO value register              */
#define GPDH            0x01B00010   /* GPIO delta high register         */
#define GPHM            0x01B00014   /* GPIO high mask register          */
#define GPDL            0x01B00018   /* GPIO delta low register          */
#define GPLM            0x01B0001C   /* GPIO low mask register           */
#define GPGC            0x01B00020   /* GPIO delta high register         */
#define GPPOL           0x01B00024   /* GPIO interrupt polarity register */


#define FLASH_START1		0x90000000
#define FLASH_START2		0x90000400
#define SOURCE_START	0x00000000
#define SOURCE_START2	0x00000400
#define DATA_LENTH1		0x00000120
#define DATA_LENTH2		0x00010730