cx88-tvaudio.c

底层驱动开发

		{ AUD_DMD_RA_DDS, 0x0F5C285 },
		{ AUD_PLL_INT, 0x1E },
		{ AUD_PLL_DDS, 0x0 },
		{ AUD_PLL_FRAC, 0x0E542 },

		// setup QAM registers
		{ AUD_RATE_ADJ1,      0x00000100 },
		{ AUD_RATE_ADJ2,      0x00000200 },
		{ AUD_RATE_ADJ3,      0x00000300 },
		{ AUD_RATE_ADJ4,      0x00000400 },
		{ AUD_RATE_ADJ5,      0x00000500 },
		{ AUD_RATE_THRES_DMD, 0x000000C0 },
		{ /* end of list */ },
	};

	static const struct rlist nicam_l[] = {
		// setup QAM registers
		{ AUD_RATE_ADJ1, 0x00000060 },
		{ AUD_RATE_ADJ2, 0x000000F9 },
		{ AUD_RATE_ADJ3, 0x000001CC },
		{ AUD_RATE_ADJ4, 0x000002B3 },
		{ AUD_RATE_ADJ5, 0x00000726 },
		{ AUD_DEEMPHDENOM1_R, 0x0000F3D0 },
		{ AUD_DEEMPHDENOM2_R, 0x00000000 },
		{ AUD_ERRLOGPERIOD_R, 0x00000064 },
		{ AUD_ERRINTRPTTHSHLD1_R, 0x00000FFF },
		{ AUD_ERRINTRPTTHSHLD2_R, 0x0000001F },
		{ AUD_ERRINTRPTTHSHLD3_R, 0x0000000F },
		{ AUD_POLYPH80SCALEFAC, 0x00000003 },
		{ AUD_DMD_RA_DDS, 0x00C00000 },
		{ AUD_PLL_INT, 0x0000001E },
		{ AUD_PLL_DDS, 0x00000000 },
		{ AUD_PLL_FRAC, 0x0000E542 },
		{ AUD_START_TIMER, 0x00000000 },
		{ AUD_DEEMPHNUMER1_R, 0x000353DE },
		{ AUD_DEEMPHNUMER2_R, 0x000001B1 },
		{ AUD_PDF_DDS_CNST_BYTE2, 0x06 },
		{ AUD_PDF_DDS_CNST_BYTE1, 0x82 },
		{ AUD_QAM_MODE, 0x05 },
		{ AUD_PDF_DDS_CNST_BYTE0, 0x12 },
		{ AUD_PHACC_FREQ_8MSB, 0x34 },
		{ AUD_PHACC_FREQ_8LSB, 0x4C },
		{ AUD_DEEMPHGAIN_R, 0x00006680 },
		{ AUD_RATE_THRES_DMD, 0x000000C0  },
		{ /* end of list */ },
	} ;
	dprintk("%s (status: devel), stereo : %d\n",__FUNCTION__,stereo);

	if (!stereo) {
	/* AM Mono */
		set_audio_start(core, SEL_A2);
		set_audio_registers(core, nicam_l_mono);
	set_audio_finish(core, EN_A2_FORCE_MONO1);
	} else {
	/* Nicam Stereo */
		set_audio_start(core, SEL_NICAM);
		set_audio_registers(core, nicam_l);
	set_audio_finish(core, 0x1924); /* FIXME */
	}
}

static void set_audio_standard_PAL_I(struct cx88_core *core, int stereo)
{
       static const struct rlist pal_i_fm_mono[] = {
	{AUD_ERRLOGPERIOD_R,       0x00000064},
	{AUD_ERRINTRPTTHSHLD1_R,   0x00000fff},
	{AUD_ERRINTRPTTHSHLD2_R,   0x0000001f},
	{AUD_ERRINTRPTTHSHLD3_R,   0x0000000f},
	{AUD_PDF_DDS_CNST_BYTE2,   0x06},
	{AUD_PDF_DDS_CNST_BYTE1,   0x82},
	{AUD_PDF_DDS_CNST_BYTE0,   0x12},
	{AUD_QAM_MODE,             0x05},
	{AUD_PHACC_FREQ_8MSB,      0x3a},
	{AUD_PHACC_FREQ_8LSB,      0x93},
	{AUD_DMD_RA_DDS,           0x002a4f2f},
	{AUD_PLL_INT,              0x0000001e},
	{AUD_PLL_DDS,              0x00000004},
	{AUD_PLL_FRAC,             0x0000e542},
	{AUD_RATE_ADJ1,            0x00000100},
	{AUD_RATE_ADJ2,            0x00000200},
	{AUD_RATE_ADJ3,            0x00000300},
	{AUD_RATE_ADJ4,            0x00000400},
	{AUD_RATE_ADJ5,            0x00000500},
	{AUD_THR_FR,               0x00000000},
	{AUD_PILOT_BQD_1_K0,       0x0000755b},
	{AUD_PILOT_BQD_1_K1,       0x00551340},
	{AUD_PILOT_BQD_1_K2,       0x006d30be},
	{AUD_PILOT_BQD_1_K3,       0xffd394af},
	{AUD_PILOT_BQD_1_K4,       0x00400000},
	{AUD_PILOT_BQD_2_K0,       0x00040000},
	{AUD_PILOT_BQD_2_K1,       0x002a4841},
	{AUD_PILOT_BQD_2_K2,       0x00400000},
	{AUD_PILOT_BQD_2_K3,       0x00000000},
	{AUD_PILOT_BQD_2_K4,       0x00000000},
	{AUD_MODE_CHG_TIMER,       0x00000060},
	{AUD_AFE_12DB_EN,          0x00000001},
	{AAGC_HYST,                0x0000000a},
	{AUD_CORDIC_SHIFT_0,       0x00000007},
	{AUD_CORDIC_SHIFT_1,       0x00000007},
	{AUD_C1_UP_THR,            0x00007000},
	{AUD_C1_LO_THR,            0x00005400},
	{AUD_C2_UP_THR,            0x00005400},
	{AUD_C2_LO_THR,            0x00003000},
	{AUD_DCOC_0_SRC,           0x0000001a},
	{AUD_DCOC0_SHIFT,          0x00000000},
	{AUD_DCOC_0_SHIFT_IN0,     0x0000000a},
	{AUD_DCOC_0_SHIFT_IN1,     0x00000008},
	{AUD_DCOC_PASS_IN,         0x00000003},
	{AUD_IIR3_0_SEL,           0x00000021},
	{AUD_DN2_AFC,              0x00000002},
	{AUD_DCOC_1_SRC,           0x0000001b},
	{AUD_DCOC1_SHIFT,          0x00000000},
	{AUD_DCOC_1_SHIFT_IN0,     0x0000000a},
	{AUD_DCOC_1_SHIFT_IN1,     0x00000008},
	{AUD_IIR3_1_SEL,           0x00000023},
	{AUD_DN0_FREQ,             0x000035a3},
	{AUD_DN2_FREQ,             0x000029c7},
	{AUD_CRDC0_SRC_SEL,        0x00000511},
	{AUD_IIR1_0_SEL,           0x00000001},
	{AUD_IIR1_1_SEL,           0x00000000},
	{AUD_IIR3_2_SEL,           0x00000003},
	{AUD_IIR3_2_SHIFT,         0x00000000},
	{AUD_IIR3_0_SEL,           0x00000002},
	{AUD_IIR2_0_SEL,           0x00000021},
	{AUD_IIR2_0_SHIFT,         0x00000002},
	{AUD_DEEMPH0_SRC_SEL,      0x0000000b},
	{AUD_DEEMPH1_SRC_SEL,      0x0000000b},
	{AUD_POLYPH80SCALEFAC,     0x00000001},
	{AUD_START_TIMER,          0x00000000},
	{ /* end of list */ },
       };

       static const struct rlist pal_i_nicam[] = {
	{ AUD_RATE_ADJ1,           0x00000010 },
	{ AUD_RATE_ADJ2,           0x00000040 },
	{ AUD_RATE_ADJ3,           0x00000100 },
	{ AUD_RATE_ADJ4,           0x00000400 },
	{ AUD_RATE_ADJ5,           0x00001000 },
	//     { AUD_DMD_RA_DDS,          0x00c0d5ce },
	{ AUD_DEEMPHGAIN_R,        0x000023c2 },
	{ AUD_DEEMPHNUMER1_R,      0x0002a7bc },
	{ AUD_DEEMPHNUMER2_R,      0x0003023e },
	{ AUD_DEEMPHDENOM1_R,      0x0000f3d0 },
	{ AUD_DEEMPHDENOM2_R,      0x00000000 },
	{ AUD_DEEMPHDENOM2_R,      0x00000000 },
	{ AUD_ERRLOGPERIOD_R,      0x00000fff },
	{ AUD_ERRINTRPTTHSHLD1_R,  0x000003ff },
	{ AUD_ERRINTRPTTHSHLD2_R,  0x000000ff },
	{ AUD_ERRINTRPTTHSHLD3_R,  0x0000003f },
	{ AUD_POLYPH80SCALEFAC,    0x00000003 },
	{ AUD_PDF_DDS_CNST_BYTE2,  0x06 },
	{ AUD_PDF_DDS_CNST_BYTE1,  0x82 },
	{ AUD_PDF_DDS_CNST_BYTE0,  0x16 },
	{ AUD_QAM_MODE,            0x05 },
	{ AUD_PDF_DDS_CNST_BYTE0,  0x12 },
	{ AUD_PHACC_FREQ_8MSB,     0x3a },
	{ AUD_PHACC_FREQ_8LSB,     0x93 },
	{ /* end of list */ },
	};

	dprintk("%s (status: devel), stereo : %d\n",__FUNCTION__,stereo);

	if (!stereo) {
	/* FM Mono */
	set_audio_start(core, SEL_A2);
		set_audio_registers(core, pal_i_fm_mono);
		set_audio_finish(core, EN_DMTRX_SUMDIFF | EN_A2_FORCE_MONO1);
	} else {
	/* Nicam Stereo */
	set_audio_start(core, SEL_NICAM);
		set_audio_registers(core, pal_i_nicam);
		set_audio_finish(core, EN_DMTRX_LR | EN_DMTRX_BYPASS | EN_NICAM_AUTO_STEREO);
	}
}

static void set_audio_standard_A2(struct cx88_core *core, u32 mode)
{
	static const struct rlist a2_common[] = {
	{AUD_ERRLOGPERIOD_R,            0x00000064},
	{AUD_ERRINTRPTTHSHLD1_R,        0x00000fff},
	{AUD_ERRINTRPTTHSHLD2_R,        0x0000001f},
	{AUD_ERRINTRPTTHSHLD3_R,        0x0000000f},
	{AUD_PDF_DDS_CNST_BYTE2,        0x06},
	{AUD_PDF_DDS_CNST_BYTE1,        0x82},
	{AUD_PDF_DDS_CNST_BYTE0,        0x12},
	{AUD_QAM_MODE,                  0x05},
	{AUD_PHACC_FREQ_8MSB,           0x34},
	{AUD_PHACC_FREQ_8LSB,           0x4c},
	{AUD_RATE_ADJ1,                 0x00000100},
	{AUD_RATE_ADJ2,                 0x00000200},
	{AUD_RATE_ADJ3,                 0x00000300},
	{AUD_RATE_ADJ4,                 0x00000400},
	{AUD_RATE_ADJ5,                 0x00000500},
	{AUD_THR_FR,                    0x00000000},
	{AAGC_HYST,                     0x0000001a},
	{AUD_PILOT_BQD_1_K0,            0x0000755b},
	{AUD_PILOT_BQD_1_K1,            0x00551340},
	{AUD_PILOT_BQD_1_K2,            0x006d30be},
	{AUD_PILOT_BQD_1_K3,            0xffd394af},
	{AUD_PILOT_BQD_1_K4,            0x00400000},
	{AUD_PILOT_BQD_2_K0,            0x00040000},
	{AUD_PILOT_BQD_2_K1,            0x002a4841},
	{AUD_PILOT_BQD_2_K2,            0x00400000},
	{AUD_PILOT_BQD_2_K3,            0x00000000},
	{AUD_PILOT_BQD_2_K4,            0x00000000},
	{AUD_MODE_CHG_TIMER,            0x00000040},
	{AUD_AFE_12DB_EN,               0x00000001},
	{AUD_CORDIC_SHIFT_0,            0x00000007},
	{AUD_CORDIC_SHIFT_1,            0x00000007},
	{AUD_DEEMPH0_G0,                0x00000380},
	{AUD_DEEMPH1_G0,                0x00000380},
	{AUD_DCOC_0_SRC,                0x0000001a},
	{AUD_DCOC0_SHIFT,               0x00000000},
	{AUD_DCOC_0_SHIFT_IN0,          0x0000000a},
	{AUD_DCOC_0_SHIFT_IN1,          0x00000008},
	{AUD_DCOC_PASS_IN,              0x00000003},
	{AUD_IIR3_0_SEL,                0x00000021},
	{AUD_DN2_AFC,                   0x00000002},
	{AUD_DCOC_1_SRC,                0x0000001b},
	{AUD_DCOC1_SHIFT,               0x00000000},
	{AUD_DCOC_1_SHIFT_IN0,          0x0000000a},
	{AUD_DCOC_1_SHIFT_IN1,          0x00000008},
	{AUD_IIR3_1_SEL,                0x00000023},
	{AUD_RDSI_SEL,                  0x00000017},
	{AUD_RDSI_SHIFT,                0x00000000},
	{AUD_RDSQ_SEL,                  0x00000017},
	{AUD_RDSQ_SHIFT,                0x00000000},
	{AUD_PLL_INT,                   0x0000001e},
	{AUD_PLL_DDS,                   0x00000000},
	{AUD_PLL_FRAC,                  0x0000e542},
	{AUD_POLYPH80SCALEFAC,          0x00000001},
	{AUD_START_TIMER,               0x00000000},
	{ /* end of list */ },
	};

	static const struct rlist a2_bg[] = {
	{AUD_DMD_RA_DDS,                0x002a4f2f},
	{AUD_C1_UP_THR,                 0x00007000},
	{AUD_C1_LO_THR,                 0x00005400},
	{AUD_C2_UP_THR,                 0x00005400},
	{AUD_C2_LO_THR,                 0x00003000},
		{ /* end of list */ },
	};

	static const struct rlist a2_dk[] = {
	{AUD_DMD_RA_DDS,                0x002a4f2f},
	{AUD_C1_UP_THR,                 0x00007000},
	{AUD_C1_LO_THR,                 0x00005400},
	{AUD_C2_UP_THR,                 0x00005400},
	{AUD_C2_LO_THR,                 0x00003000},
	{AUD_DN0_FREQ,                  0x00003a1c},
	{AUD_DN2_FREQ,                  0x0000d2e0},
		{ /* end of list */ },
	};
/* unknown, probably NTSC-M */
	static const struct rlist a2_m[] = {
	{AUD_DMD_RA_DDS,                0x002a0425},
	{AUD_C1_UP_THR,                 0x00003c00},
	{AUD_C1_LO_THR,                 0x00003000},
	{AUD_C2_UP_THR,                 0x00006000},
	{AUD_C2_LO_THR,                 0x00003c00},
	{AUD_DEEMPH0_A0,                0x00007a80},
	{AUD_DEEMPH1_A0,                0x00007a80},
	{AUD_DEEMPH0_G0,                0x00001200},
	{AUD_DEEMPH1_G0,                0x00001200},
	{AUD_DN0_FREQ,                  0x0000283b},
	{AUD_DN1_FREQ,                  0x00003418},
	{AUD_DN2_FREQ,                  0x000029c7},
	{AUD_POLY0_DDS_CONSTANT,        0x000a7540},
		{ /* end of list */ },
	};

	static const struct rlist a2_deemph50[] = {
	{AUD_DEEMPH0_G0,                0x00000380},
	{AUD_DEEMPH1_G0,                0x00000380},
	{AUD_DEEMPHGAIN_R,              0x000011e1},
	{AUD_DEEMPHNUMER1_R,            0x0002a7bc},
	{AUD_DEEMPHNUMER2_R,            0x0003023c},
	{ /* end of list */ },
	};

	static const struct rlist a2_deemph75[] = {
	{AUD_DEEMPH0_G0,                0x00000480},
	{AUD_DEEMPH1_G0,                0x00000480},
	{AUD_DEEMPHGAIN_R,              0x00009000},
	{AUD_DEEMPHNUMER1_R,            0x000353de},
	{AUD_DEEMPHNUMER2_R,            0x000001b1},
		{ /* end of list */ },
	};

	set_audio_start(core, SEL_A2);
	set_audio_registers(core, a2_common);
	switch (core->tvaudio) {
	case WW_A2_BG:
		dprintk("%s PAL-BG A2 (status: known-good)\n",__FUNCTION__);
	set_audio_registers(core, a2_bg);
	set_audio_registers(core, a2_deemph50);
		break;
	case WW_A2_DK:
		dprintk("%s PAL-DK A2 (status: known-good)\n",__FUNCTION__);
	set_audio_registers(core, a2_dk);
	set_audio_registers(core, a2_deemph50);
		break;
	case WW_A2_M:
		dprintk("%s NTSC-M A2 (status: unknown)\n",__FUNCTION__);
	set_audio_registers(core, a2_m);
	set_audio_registers(core, a2_deemph75);
		break;
	};

	mode |= EN_FMRADIO_EN_RDS | EN_DMTRX_SUMDIFF;
	set_audio_finish(core, mode);
}

static void set_audio_standard_EIAJ(struct cx88_core *core)
{
	static const struct rlist eiaj[] = {
		/* TODO: eiaj register settings are not there yet ... */

		{ /* end of list */ },
	};
	dprintk("%s (status: unknown)\n",__FUNCTION__);

	set_audio_start(core, SEL_EIAJ);
	set_audio_registers(core, eiaj);
	set_audio_finish(core, EN_EIAJ_AUTO_STEREO);
}

static void set_audio_standard_FM(struct cx88_core *core, enum cx88_deemph_type deemph)
{
	static const struct rlist fm_deemph_50[] = {
		{ AUD_DEEMPH0_G0,	0x0C45 },
		{ AUD_DEEMPH0_A0,	0x6262 },
		{ AUD_DEEMPH0_B0,	0x1C29 },
		{ AUD_DEEMPH0_A1,	0x3FC66},
		{ AUD_DEEMPH0_B1,	0x399A },