cx88-tvaudio.c

底层驱动开发

/*

    cx88x-audio.c - Conexant CX23880/23881 audio downstream driver driver

     (c) 2001 Michael Eskin, Tom Zakrajsek [Windows version]
     (c) 2002 Yurij Sysoev <[e-mail]>
     (c) 2003 Gerd Knorr <[e-mail]>

    -----------------------------------------------------------------------

    Lot of voodoo here.  Even the data sheet doesn't help to
    understand what is going on here, the documentation for the audio
    part of the cx2388x chip is *very* bad.

    Some of this comes from party done linux driver sources I got from
    [undocumented].

    Some comes from the dscaler sources, one of the dscaler driver guy works
    for Conexant ...

    -----------------------------------------------------------------------

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/poll.h>
#include <linux/pci.h>
#include <linux/signal.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/vmalloc.h>
#include <linux/init.h>
#include <linux/smp_lock.h>
#include <linux/delay.h>
#include <linux/kthread.h>

#include "cx88.h"

static unsigned int audio_debug = 0;
module_param(audio_debug,int,0644);
MODULE_PARM_DESC(audio_debug,"enable debug messages [audio]");

#define dprintk(fmt, arg...)	if (audio_debug) \
	printk(KERN_DEBUG "%s/0: " fmt, core->name , ## arg)

/* ----------------------------------------------------------- */

static char *aud_ctl_names[64] =
{
	[ EN_BTSC_FORCE_MONO       ] = "BTSC_FORCE_MONO",
	[ EN_BTSC_FORCE_STEREO     ] = "BTSC_FORCE_STEREO",
	[ EN_BTSC_FORCE_SAP        ] = "BTSC_FORCE_SAP",
	[ EN_BTSC_AUTO_STEREO      ] = "BTSC_AUTO_STEREO",
	[ EN_BTSC_AUTO_SAP         ] = "BTSC_AUTO_SAP",
	[ EN_A2_FORCE_MONO1        ] = "A2_FORCE_MONO1",
	[ EN_A2_FORCE_MONO2        ] = "A2_FORCE_MONO2",
	[ EN_A2_FORCE_STEREO       ] = "A2_FORCE_STEREO",
	[ EN_A2_AUTO_MONO2         ] = "A2_AUTO_MONO2",
	[ EN_A2_AUTO_STEREO        ] = "A2_AUTO_STEREO",
	[ EN_EIAJ_FORCE_MONO1      ] = "EIAJ_FORCE_MONO1",
	[ EN_EIAJ_FORCE_MONO2      ] = "EIAJ_FORCE_MONO2",
	[ EN_EIAJ_FORCE_STEREO     ] = "EIAJ_FORCE_STEREO",
	[ EN_EIAJ_AUTO_MONO2       ] = "EIAJ_AUTO_MONO2",
	[ EN_EIAJ_AUTO_STEREO      ] = "EIAJ_AUTO_STEREO",
	[ EN_NICAM_FORCE_MONO1     ] = "NICAM_FORCE_MONO1",
	[ EN_NICAM_FORCE_MONO2     ] = "NICAM_FORCE_MONO2",
	[ EN_NICAM_FORCE_STEREO    ] = "NICAM_FORCE_STEREO",
	[ EN_NICAM_AUTO_MONO2      ] = "NICAM_AUTO_MONO2",
	[ EN_NICAM_AUTO_STEREO     ] = "NICAM_AUTO_STEREO",
	[ EN_FMRADIO_FORCE_MONO    ] = "FMRADIO_FORCE_MONO",
	[ EN_FMRADIO_FORCE_STEREO  ] = "FMRADIO_FORCE_STEREO",
	[ EN_FMRADIO_AUTO_STEREO   ] = "FMRADIO_AUTO_STEREO",
};

struct rlist {
	u32 reg;
	u32 val;
};

static void set_audio_registers(struct cx88_core *core,
				const struct rlist *l)
{
	int i;

	for (i = 0; l[i].reg; i++) {
		switch (l[i].reg) {
		case AUD_PDF_DDS_CNST_BYTE2:
		case AUD_PDF_DDS_CNST_BYTE1:
		case AUD_PDF_DDS_CNST_BYTE0:
		case AUD_QAM_MODE:
		case AUD_PHACC_FREQ_8MSB:
		case AUD_PHACC_FREQ_8LSB:
			cx_writeb(l[i].reg, l[i].val);
			break;
		default:
			cx_write(l[i].reg, l[i].val);
			break;
		}
	}
}

static void set_audio_start(struct cx88_core *core,
			u32 mode)
{
	// mute
	cx_write(AUD_VOL_CTL,       (1 << 6));

	// start programming
	cx_write(AUD_CTL,           0x0000);
	cx_write(AUD_INIT,          mode);
	cx_write(AUD_INIT_LD,       0x0001);
	cx_write(AUD_SOFT_RESET,    0x0001);
}

static void set_audio_finish(struct cx88_core *core, u32 ctl)
{
	u32 volume;

	if (cx88_boards[core->board].blackbird) {
		// sets sound input from external adc
		cx_set(AUD_CTL, EN_I2SIN_ENABLE);
		//cx_write(AUD_I2SINPUTCNTL, 0);
		cx_write(AUD_I2SINPUTCNTL, 4);
		cx_write(AUD_BAUDRATE, 1);
		// 'pass-thru mode': this enables the i2s output to the mpeg encoder
		cx_set(AUD_CTL, EN_I2SOUT_ENABLE);
		cx_write(AUD_I2SOUTPUTCNTL, 1);
		cx_write(AUD_I2SCNTL, 0);
		//cx_write(AUD_APB_IN_RATE_ADJ, 0);
	} else {
	ctl |= EN_DAC_ENABLE;
	cx_write(AUD_CTL, ctl);
	}

	/* finish programming */
	cx_write(AUD_SOFT_RESET, 0x0000);

	/* unmute */
	volume = cx_sread(SHADOW_AUD_VOL_CTL);
	cx_swrite(SHADOW_AUD_VOL_CTL, AUD_VOL_CTL, volume);
}

/* ----------------------------------------------------------- */

static void set_audio_standard_BTSC(struct cx88_core *core, unsigned int sap, u32 mode)
{
	static const struct rlist btsc[] = {
	{ AUD_AFE_12DB_EN,             0x00000001 },
		{ AUD_OUT1_SEL,                0x00000013 },
		{ AUD_OUT1_SHIFT,              0x00000000 },
		{ AUD_POLY0_DDS_CONSTANT,      0x0012010c },
		{ AUD_DMD_RA_DDS,              0x00c3e7aa },
		{ AUD_DBX_IN_GAIN,             0x00004734 },
		{ AUD_DBX_WBE_GAIN,            0x00004640 },
		{ AUD_DBX_SE_GAIN,             0x00008d31 },
		{ AUD_DCOC_0_SRC,              0x0000001a },
		{ AUD_IIR1_4_SEL,              0x00000021 },
		{ AUD_DCOC_PASS_IN,            0x00000003 },
		{ AUD_DCOC_0_SHIFT_IN0,        0x0000000a },
		{ AUD_DCOC_0_SHIFT_IN1,        0x00000008 },
		{ AUD_DCOC_1_SHIFT_IN0,        0x0000000a },
		{ AUD_DCOC_1_SHIFT_IN1,        0x00000008 },
		{ AUD_DN0_FREQ,                0x0000283b },
		{ AUD_DN2_SRC_SEL,             0x00000008 },
		{ AUD_DN2_FREQ,                0x00003000 },
		{ AUD_DN2_AFC,                 0x00000002 },
		{ AUD_DN2_SHFT,                0x00000000 },
		{ AUD_IIR2_2_SEL,              0x00000020 },
		{ AUD_IIR2_2_SHIFT,            0x00000000 },
		{ AUD_IIR2_3_SEL,              0x0000001f },
		{ AUD_IIR2_3_SHIFT,            0x00000000 },
		{ AUD_CRDC1_SRC_SEL,           0x000003ce },
		{ AUD_CRDC1_SHIFT,             0x00000000 },
		{ AUD_CORDIC_SHIFT_1,          0x00000007 },
		{ AUD_DCOC_1_SRC,              0x0000001b },
		{ AUD_DCOC1_SHIFT,             0x00000000 },
		{ AUD_RDSI_SEL,                0x00000008 },
		{ AUD_RDSQ_SEL,                0x00000008 },
		{ AUD_RDSI_SHIFT,              0x00000000 },
		{ AUD_RDSQ_SHIFT,              0x00000000 },
		{ AUD_POLYPH80SCALEFAC,        0x00000003 },
		{ /* end of list */ },
	};
	static const struct rlist btsc_sap[] = {
	{ AUD_AFE_12DB_EN,             0x00000001 },
		{ AUD_DBX_IN_GAIN,             0x00007200 },
		{ AUD_DBX_WBE_GAIN,            0x00006200 },
		{ AUD_DBX_SE_GAIN,             0x00006200 },
		{ AUD_IIR1_1_SEL,              0x00000000 },
		{ AUD_IIR1_3_SEL,              0x00000001 },
		{ AUD_DN1_SRC_SEL,             0x00000007 },
		{ AUD_IIR1_4_SHIFT,            0x00000006 },
		{ AUD_IIR2_1_SHIFT,            0x00000000 },
		{ AUD_IIR2_2_SHIFT,            0x00000000 },
		{ AUD_IIR3_0_SHIFT,            0x00000000 },
		{ AUD_IIR3_1_SHIFT,            0x00000000 },
		{ AUD_IIR3_0_SEL,              0x0000000d },
		{ AUD_IIR3_1_SEL,              0x0000000e },
		{ AUD_DEEMPH1_SRC_SEL,         0x00000014 },
		{ AUD_DEEMPH1_SHIFT,           0x00000000 },
		{ AUD_DEEMPH1_G0,              0x00004000 },
		{ AUD_DEEMPH1_A0,              0x00000000 },
		{ AUD_DEEMPH1_B0,              0x00000000 },
		{ AUD_DEEMPH1_A1,              0x00000000 },
		{ AUD_DEEMPH1_B1,              0x00000000 },
		{ AUD_OUT0_SEL,                0x0000003f },
		{ AUD_OUT1_SEL,                0x0000003f },
		{ AUD_DN1_AFC,                 0x00000002 },
		{ AUD_DCOC_0_SHIFT_IN0,        0x0000000a },
		{ AUD_DCOC_0_SHIFT_IN1,        0x00000008 },
		{ AUD_DCOC_1_SHIFT_IN0,        0x0000000a },
		{ AUD_DCOC_1_SHIFT_IN1,        0x00000008 },
		{ AUD_IIR1_0_SEL,              0x0000001d },
		{ AUD_IIR1_2_SEL,              0x0000001e },
		{ AUD_IIR2_1_SEL,              0x00000002 },
		{ AUD_IIR2_2_SEL,              0x00000004 },
		{ AUD_IIR3_2_SEL,              0x0000000f },
		{ AUD_DCOC2_SHIFT,             0x00000001 },
		{ AUD_IIR3_2_SHIFT,            0x00000001 },
		{ AUD_DEEMPH0_SRC_SEL,         0x00000014 },
		{ AUD_CORDIC_SHIFT_1,          0x00000006 },
		{ AUD_POLY0_DDS_CONSTANT,      0x000e4db2 },
		{ AUD_DMD_RA_DDS,              0x00f696e6 },
		{ AUD_IIR2_3_SEL,              0x00000025 },
		{ AUD_IIR1_4_SEL,              0x00000021 },
		{ AUD_DN1_FREQ,                0x0000c965 },
		{ AUD_DCOC_PASS_IN,            0x00000003 },
		{ AUD_DCOC_0_SRC,              0x0000001a },
		{ AUD_DCOC_1_SRC,              0x0000001b },
		{ AUD_DCOC1_SHIFT,             0x00000000 },
		{ AUD_RDSI_SEL,                0x00000009 },
		{ AUD_RDSQ_SEL,                0x00000009 },
		{ AUD_RDSI_SHIFT,              0x00000000 },
		{ AUD_RDSQ_SHIFT,              0x00000000 },
		{ AUD_POLYPH80SCALEFAC,        0x00000003 },
		{ /* end of list */ },
	};

	mode |= EN_FMRADIO_EN_RDS;

	if (sap) {
		dprintk("%s SAP (status: unknown)\n",__FUNCTION__);
	set_audio_start(core, SEL_SAP);
		set_audio_registers(core, btsc_sap);
		set_audio_finish(core, mode);
	} else {
		dprintk("%s (status: known-good)\n",__FUNCTION__);
	set_audio_start(core, SEL_BTSC);
		set_audio_registers(core, btsc);
		set_audio_finish(core, mode);
	}
}


static void set_audio_standard_NICAM_L(struct cx88_core *core, int stereo)
{
	/* This is probably weird..
	* Let's operate and find out. */

	static const struct rlist nicam_l_mono[] = {
		{ AUD_ERRLOGPERIOD_R,     0x00000064 },
		{ AUD_ERRINTRPTTHSHLD1_R, 0x00000FFF },
		{ AUD_ERRINTRPTTHSHLD2_R, 0x0000001F },
		{ AUD_ERRINTRPTTHSHLD3_R, 0x0000000F },

		{ AUD_PDF_DDS_CNST_BYTE2, 0x48 },
		{ AUD_PDF_DDS_CNST_BYTE1, 0x3D },
		{ AUD_QAM_MODE,           0x00 },
		{ AUD_PDF_DDS_CNST_BYTE0, 0xf5 },
		{ AUD_PHACC_FREQ_8MSB,    0x3a },
		{ AUD_PHACC_FREQ_8LSB,    0x4a },

		{ AUD_DEEMPHGAIN_R, 0x6680 },
		{ AUD_DEEMPHNUMER1_R, 0x353DE },
		{ AUD_DEEMPHNUMER2_R, 0x1B1 },
		{ AUD_DEEMPHDENOM1_R, 0x0F3D0 },
		{ AUD_DEEMPHDENOM2_R, 0x0 },
		{ AUD_FM_MODE_ENABLE, 0x7 },
		{ AUD_POLYPH80SCALEFAC, 0x3 },
		{ AUD_AFE_12DB_EN, 0x1 },
		{ AAGC_GAIN, 0x0 },
		{ AAGC_HYST, 0x18 },
		{ AAGC_DEF, 0x20 },
		{ AUD_DN0_FREQ, 0x0 },
		{ AUD_POLY0_DDS_CONSTANT, 0x0E4DB2 },
		{ AUD_DCOC_0_SRC, 0x21 },
		{ AUD_IIR1_0_SEL, 0x0 },
		{ AUD_IIR1_0_SHIFT, 0x7 },
		{ AUD_IIR1_1_SEL, 0x2 },
		{ AUD_IIR1_1_SHIFT, 0x0 },
		{ AUD_DCOC_1_SRC, 0x3 },
		{ AUD_DCOC1_SHIFT, 0x0 },
		{ AUD_DCOC_PASS_IN, 0x0 },
		{ AUD_IIR1_2_SEL, 0x23 },
		{ AUD_IIR1_2_SHIFT, 0x0 },
		{ AUD_IIR1_3_SEL, 0x4 },
		{ AUD_IIR1_3_SHIFT, 0x7 },
		{ AUD_IIR1_4_SEL, 0x5 },
		{ AUD_IIR1_4_SHIFT, 0x7 },
		{ AUD_IIR3_0_SEL, 0x7 },
		{ AUD_IIR3_0_SHIFT, 0x0 },
		{ AUD_DEEMPH0_SRC_SEL, 0x11 },
		{ AUD_DEEMPH0_SHIFT, 0x0 },
		{ AUD_DEEMPH0_G0, 0x7000 },
		{ AUD_DEEMPH0_A0, 0x0 },
		{ AUD_DEEMPH0_B0, 0x0 },
		{ AUD_DEEMPH0_A1, 0x0 },
		{ AUD_DEEMPH0_B1, 0x0 },
		{ AUD_DEEMPH1_SRC_SEL, 0x11 },
		{ AUD_DEEMPH1_SHIFT, 0x0 },
		{ AUD_DEEMPH1_G0, 0x7000 },
		{ AUD_DEEMPH1_A0, 0x0 },
		{ AUD_DEEMPH1_B0, 0x0 },
		{ AUD_DEEMPH1_A1, 0x0 },
		{ AUD_DEEMPH1_B1, 0x0 },
		{ AUD_OUT0_SEL, 0x3F },
		{ AUD_OUT1_SEL, 0x3F },