cache.c

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	/* Since this is used inside ptrace, the ASID in the mm context
	   typically won't match current_asid.  We'll have to switch ASID to do
	   this.  For safety, and given that the range will be small, do all
	   this under cli.

	   Note, there is a hazard that the ASID in mm->context is no longer
	   actually associated with mm, i.e. if the mm->context has started a
	   new cycle since mm was last active.  However, this is just a
	   performance issue: all that happens is that we invalidate lines
	   belonging to another mm, so the owning process has to refill them
	   when that mm goes live again.  mm itself can't have any cache
	   entries because there will have been a flush_cache_all when the new
	   mm->context cycle started. */

	/* Align to start of cache line.  Otherwise, suppose len==8 and start
	   was at 32N+28 : the last 4 bytes wouldn't get invalidated. */
	eaddr = start & L1_CACHE_ALIGN_MASK;
	eaddr_end = start + len;

	local_irq_save(flags);
	mm_asid = mm->context & MMU_CONTEXT_ASID_MASK;
	current_asid = switch_and_save_asid(mm_asid);

	epage_start = eaddr & PAGE_MASK;

	while (eaddr < eaddr_end)
	{
		asm __volatile__("icbi %0, 0" : : "r" (eaddr));
		eaddr += L1_CACHE_BYTES;
	}
	switch_and_save_asid(current_asid);
	local_irq_restore(flags);
}

static void sh64_icache_inv_current_user_range(unsigned long start, unsigned long end)
{
	/* The icbi instruction never raises ITLBMISS.  i.e. if there's not a
	   cache hit on the virtual tag the instruction ends there, without a
	   TLB lookup. */

	unsigned long long aligned_start;
	unsigned long long ull_end;
	unsigned long long addr;

	ull_end = end;

	/* Just invalidate over the range using the natural addresses.  TLB
	   miss handling will be OK (TBC).  Since it's for the current process,
	   either we're already in the right ASID context, or the ASIDs have
	   been recycled since we were last active in which case we might just
	   invalidate another processes I-cache entries : no worries, just a
	   performance drop for him. */
	aligned_start = start & L1_CACHE_ALIGN_MASK;
	addr = aligned_start;
	while (addr < ull_end) {
		asm __volatile__ ("icbi %0, 0" : : "r" (addr));
		asm __volatile__ ("nop");
		asm __volatile__ ("nop");
		addr += L1_CACHE_BYTES;
	}
}

#endif /* !CONFIG_ICACHE_DISABLED */

/****************************************************************************/

#ifndef CONFIG_DCACHE_DISABLED

/* Buffer used as the target of alloco instructions to purge data from cache
   sets by natural eviction. -- RPC */
#define DUMMY_ALLOCO_AREA_SIZE L1_CACHE_SIZE_BYTES + (1024 * 4)
static unsigned char dummy_alloco_area[DUMMY_ALLOCO_AREA_SIZE] __cacheline_aligned = { 0, };

/****************************************************************************/

static void __inline__ sh64_dcache_purge_sets(int sets_to_purge_base, int n_sets)
{
	/* Purge all ways in a particular block of sets, specified by the base
	   set number and number of sets.  Can handle wrap-around, if that's
	   needed.  */

	int dummy_buffer_base_set;
	unsigned long long eaddr, eaddr0, eaddr1;
	int j;
	int set_offset;

	dummy_buffer_base_set = ((int)&dummy_alloco_area & cpu_data->dcache.idx_mask) >> cpu_data->dcache.entry_shift;
	set_offset = sets_to_purge_base - dummy_buffer_base_set;

	for (j=0; j<n_sets; j++, set_offset++) {
		set_offset &= (cpu_data->dcache.sets - 1);
		eaddr0 = (unsigned long long)dummy_alloco_area + (set_offset << cpu_data->dcache.entry_shift);

		/* Do one alloco which hits the required set per cache way.  For
		   write-back mode, this will purge the #ways resident lines.   There's
		   little point unrolling this loop because the allocos stall more if
		   they're too close together. */
		eaddr1 = eaddr0 + cpu_data->dcache.way_ofs * cpu_data->dcache.ways;
		for (eaddr=eaddr0; eaddr<eaddr1; eaddr+=cpu_data->dcache.way_ofs) {
			asm __volatile__ ("alloco %0, 0" : : "r" (eaddr));
			asm __volatile__ ("synco"); /* TAKum03020 */
		}

		eaddr1 = eaddr0 + cpu_data->dcache.way_ofs * cpu_data->dcache.ways;
		for (eaddr=eaddr0; eaddr<eaddr1; eaddr+=cpu_data->dcache.way_ofs) {
			/* Load from each address.  Required because alloco is a NOP if
			   the cache is write-through.  Write-through is a config option. */
			if (test_bit(SH_CACHE_MODE_WT, &(cpu_data->dcache.flags)))
				*(volatile unsigned char *)(int)eaddr;
		}
	}

	/* Don't use OCBI to invalidate the lines.  That costs cycles directly.
	   If the dummy block is just left resident, it will naturally get
	   evicted as required.  */

	return;
}

/****************************************************************************/

static void sh64_dcache_purge_all(void)
{
	/* Purge the entire contents of the dcache.  The most efficient way to
	   achieve this is to use alloco instructions on a region of unused
	   memory equal in size to the cache, thereby causing the current
	   contents to be discarded by natural eviction.  The alternative,
	   namely reading every tag, setting up a mapping for the corresponding
	   page and doing an OCBP for the line, would be much more expensive.
	   */

	sh64_dcache_purge_sets(0, cpu_data->dcache.sets);

	return;

}

/****************************************************************************/

static void sh64_dcache_purge_kernel_range(unsigned long start, unsigned long end)
{
	/* Purge the range of addresses [start,end] from the D-cache.  The
	   addresses lie in the superpage mapping.  There's no harm if we
	   overpurge at either end - just a small performance loss. */
	unsigned long long ullend, addr, aligned_start;
#if (NEFF == 32)
	aligned_start = (unsigned long long)(signed long long)(signed long) start;
#else
#error "NEFF != 32"
#endif
	aligned_start &= L1_CACHE_ALIGN_MASK;
	addr = aligned_start;
#if (NEFF == 32)
	ullend = (unsigned long long) (signed long long) (signed long) end;
#else
#error "NEFF != 32"
#endif
	while (addr <= ullend) {
		asm __volatile__ ("ocbp %0, 0" : : "r" (addr));
		addr += L1_CACHE_BYTES;
	}
	return;
}

/* Assumes this address (+ (2**n_synbits) pages up from it) aren't used for
   anything else in the kernel */
#define MAGIC_PAGE0_START 0xffffffffec000000ULL

static void sh64_dcache_purge_coloured_phy_page(unsigned long paddr, unsigned long eaddr)
{
	/* Purge the physical page 'paddr' from the cache.  It's known that any
	   cache lines requiring attention have the same page colour as the the
	   address 'eaddr'.

	   This relies on the fact that the D-cache matches on physical tags
	   when no virtual tag matches.  So we create an alias for the original
	   page and purge through that.  (Alternatively, we could have done
	   this by switching ASID to match the original mapping and purged
	   through that, but that involves ASID switching cost + probably a
	   TLBMISS + refill anyway.)
	   */

	unsigned long long magic_page_start;
	unsigned long long magic_eaddr, magic_eaddr_end;

	magic_page_start = MAGIC_PAGE0_START + (eaddr & CACHE_OC_SYN_MASK);

	/* As long as the kernel is not pre-emptible, this doesn't need to be
	   under cli/sti. */

	sh64_setup_dtlb_cache_slot(magic_page_start, get_asid(), paddr);

	magic_eaddr = magic_page_start;
	magic_eaddr_end = magic_eaddr + PAGE_SIZE;
	while (magic_eaddr < magic_eaddr_end) {
		/* Little point in unrolling this loop - the OCBPs are blocking
		   and won't go any quicker (i.e. the loop overhead is parallel
		   to part of the OCBP execution.) */
		asm __volatile__ ("ocbp %0, 0" : : "r" (magic_eaddr));
		magic_eaddr += L1_CACHE_BYTES;
	}

	sh64_teardown_dtlb_cache_slot();
}

/****************************************************************************/

static void sh64_dcache_purge_phy_page(unsigned long paddr)
{
	/* Pure a page given its physical start address, by creating a
	   temporary 1 page mapping and purging across that.  Even if we know
	   the virtual address (& vma or mm) of the page, the method here is
	   more elegant because it avoids issues of coping with page faults on
	   the purge instructions (i.e. no special-case code required in the
	   critical path in the TLB miss handling). */

	unsigned long long eaddr_start, eaddr, eaddr_end;
	int i;

	/* As long as the kernel is not pre-emptible, this doesn't need to be
	   under cli/sti. */

	eaddr_start = MAGIC_PAGE0_START;
	for (i=0; i < (1 << CACHE_OC_N_SYNBITS); i++) {
		sh64_setup_dtlb_cache_slot(eaddr_start, get_asid(), paddr);

		eaddr = eaddr_start;
		eaddr_end = eaddr + PAGE_SIZE;
		while (eaddr < eaddr_end) {
			asm __volatile__ ("ocbp %0, 0" : : "r" (eaddr));
			eaddr += L1_CACHE_BYTES;
		}

		sh64_teardown_dtlb_cache_slot();
		eaddr_start += PAGE_SIZE;
	}
}

static void sh64_dcache_purge_user_page(struct mm_struct *mm, unsigned long eaddr)
{
	pgd_t *pgd;
	pmd_t *pmd;
	pte_t *pte;
	pte_t entry;
	unsigned long paddr;

	/* NOTE : all the callers of this have mm->page_table_lock held, so the
	   following page table traversal is safe even on SMP/pre-emptible. */

	if (!mm) return; /* No way to find physical address of page */
	pgd = pgd_offset(mm, eaddr);
	if (pgd_bad(*pgd)) return;

	pmd = pmd_offset(pgd, eaddr);
	if (pmd_none(*pmd) || pmd_bad(*pmd)) return;

	pte = pte_offset_kernel(pmd, eaddr);
	entry = *pte;
	if (pte_none(entry) || !pte_present(entry)) return;

	paddr = pte_val(entry) & PAGE_MASK;

	sh64_dcache_purge_coloured_phy_page(paddr, eaddr);

}
/****************************************************************************/

static void sh64_dcache_purge_user_range(struct mm_struct *mm,
			  unsigned long start, unsigned long end)
{
	/* There are at least 5 choices for the implementation of this, with
	   pros (+), cons(-), comments(*):

	   1. ocbp each line in the range through the original user's ASID
	      + no lines spuriously evicted
	      - tlbmiss handling (must either handle faults on demand => extra
		special-case code in tlbmiss critical path), or map the page in
		advance (=> flush_tlb_range in advance to avoid multiple hits)
	      - ASID switching
	      - expensive for large ranges

	   2. temporarily map each page in the range to a special effective
	      address and ocbp through the temporary mapping; relies on the
	      fact that SH-5 OCB* always do TLB lookup and match on ptags (they
	      never look at the etags)
	      + no spurious evictions
	      - expensive for large ranges
	      * surely cheaper than (1)

	   3. walk all the lines in the cache, check the tags, if a match
	      occurs create a page mapping to ocbp the line through
	      + no spurious evictions
	      - tag inspection overhead
	      - (especially for small ranges)
	      - potential cost of setting up/tearing down page mapping for
		every line that matches the range
	      * cost partly independent of range size

	   4. walk all the lines in the cache, check the tags, if a match
	      occurs use 4 * alloco to purge the line (+3 other probably
	      innocent victims) by natural eviction
	      + no tlb mapping overheads
	      - spurious evictions
	      - tag inspection overhead

	   5. implement like flush_cache_all
	      + no tag inspection overhead
	      - spurious evictions
	      - bad for small ranges

	   (1) can be ruled out as more expensive than (2).  (2) appears best
	   for small ranges.  The choice between (3), (4) and (5) for large
	   ranges and the range size for the large/small boundary need
	   benchmarking to determine.

	   For now use approach (2) for small ranges and (5) for large ones.

	   */

	int n_pages;

	n_pages = ((end - start) >> PAGE_SHIFT);
	if (n_pages >= 64) {
#if 1
		sh64_dcache_purge_all();
#else
		unsigned long long set, way;
		unsigned long mm_asid = mm->context & MMU_CONTEXT_ASID_MASK;
		for (set = 0; set < cpu_data->dcache.sets; set++) {
			unsigned long long set_base_config_addr = CACHE_OC_ADDRESS_ARRAY + (set << cpu_data->dcache.set_shift);
			for (way = 0; way < cpu_data->dcache.ways; way++) {
				unsigned long long config_addr = set_base_config_addr + (way << cpu_data->dcache.way_step_shift);
				unsigned long long tag0;
				unsigned long line_valid;

				asm __volatile__("getcfg %1, 0, %0" : "=r" (tag0) : "r" (config_addr));
				line_valid = tag0 & SH_CACHE_VALID;
				if (line_valid) {
					unsigned long cache_asid;
					unsigned long epn;

					cache_asid = (tag0 & cpu_data->dcache.asid_mask) >> cpu_data->dcache.asid_shift;
					/* The next line needs some
					   explanation.  The virtual tags
					   encode bits [31:13] of the virtual
					   address, bit [12] of the 'tag' being
					   implied by the cache set index. */
					epn = (tag0 & cpu_data->dcache.epn_mask) | ((set & 0x80) << cpu_data->dcache.entry_shift);