clock.c

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/*
 *  linux/arch/arm/plat-omap/clock.c
 *
 *  Copyright (C) 2004 Nokia corporation
 *  Written by Tuukka Tikkanen <[e-mail]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>

#include <asm/io.h>
#include <asm/semaphore.h>
#include <asm/hardware/clock.h>
#include <asm/arch/board.h>
#include <asm/arch/usb.h>

#include "clock.h"
#include "sram.h"

static LIST_HEAD(clocks);
static DECLARE_MUTEX(clocks_sem);
static DEFINE_SPINLOCK(clockfw_lock);
static void propagate_rate(struct clk *  clk);
/* UART clock function */
static int set_uart_rate(struct clk * clk, unsigned long rate);
/* External clock (MCLK & BCLK) functions */
static int set_ext_clk_rate(struct clk *  clk, unsigned long rate);
static long round_ext_clk_rate(struct clk *  clk, unsigned long rate);
static void init_ext_clk(struct clk *  clk);
/* MPU virtual clock functions */
static int select_table_rate(struct clk *  clk, unsigned long rate);
static long round_to_table_rate(struct clk *  clk, unsigned long rate);
void clk_setdpll(__u16, __u16);

static struct mpu_rate rate_table[] = {
	/* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
	 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
	 */
#if defined(CONFIG_OMAP_ARM_216MHZ)
	{ 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
#endif
#if defined(CONFIG_OMAP_ARM_195MHZ)
	{ 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
#endif
#if defined(CONFIG_OMAP_ARM_192MHZ)
	{ 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
	{ 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
	{  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
	{  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/8/4/4/8/8 */
	{  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
#endif
#if defined(CONFIG_OMAP_ARM_182MHZ)
	{ 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
#endif
#if defined(CONFIG_OMAP_ARM_168MHZ)
	{ 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
#endif
#if defined(CONFIG_OMAP_ARM_150MHZ)
	{ 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
#endif
#if defined(CONFIG_OMAP_ARM_120MHZ)
	{ 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
#endif
#if defined(CONFIG_OMAP_ARM_96MHZ)
	{  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
#endif
#if defined(CONFIG_OMAP_ARM_60MHZ)
	{  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
#endif
#if defined(CONFIG_OMAP_ARM_30MHZ)
	{  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
#endif
	{ 0, 0, 0, 0, 0 },
};


static void ckctl_recalc(struct clk *  clk);
int __clk_enable(struct clk *clk);
void __clk_disable(struct clk *clk);
void __clk_unuse(struct clk *clk);
int __clk_use(struct clk *clk);


static void followparent_recalc(struct clk *  clk)
{
	clk->rate = clk->parent->rate;
}


static void watchdog_recalc(struct clk *  clk)
{
	clk->rate = clk->parent->rate / 14;
}

static void uart_recalc(struct clk * clk)
{
	unsigned int val = omap_readl(clk->enable_reg);
	if (val & clk->enable_bit)
		clk->rate = 48000000;
	else
		clk->rate = 12000000;
}

static struct clk ck_ref = {
	.name		= "ck_ref",
	.rate		= 12000000,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
			  ALWAYS_ENABLED,
};

static struct clk ck_dpll1 = {
	.name		= "ck_dpll1",
	.parent		= &ck_ref,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
			  RATE_PROPAGATES | ALWAYS_ENABLED,
};

static struct clk ck_dpll1out = {
	.name		= "ck_dpll1out",
	.parent		= &ck_dpll1,
	.flags		= CLOCK_IN_OMAP16XX,
	.enable_reg	= ARM_IDLECT2,
	.enable_bit	= EN_CKOUT_ARM,
	.recalc		= &followparent_recalc,
};

static struct clk arm_ck = {
	.name		= "arm_ck",
	.parent		= &ck_dpll1,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
			  RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
	.rate_offset	= CKCTL_ARMDIV_OFFSET,
	.recalc		= &ckctl_recalc,
};

static struct clk armper_ck = {
	.name		= "armper_ck",
	.parent		= &ck_dpll1,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
			  RATE_CKCTL,
	.enable_reg	= ARM_IDLECT2,
	.enable_bit	= EN_PERCK,
	.rate_offset	= CKCTL_PERDIV_OFFSET,
	.recalc		= &ckctl_recalc,
};

static struct clk arm_gpio_ck = {
	.name		= "arm_gpio_ck",
	.parent		= &ck_dpll1,
	.flags		= CLOCK_IN_OMAP1510,
	.enable_reg	= ARM_IDLECT2,
	.enable_bit	= EN_GPIOCK,
	.recalc		= &followparent_recalc,
};

static struct clk armxor_ck = {
	.name		= "armxor_ck",
	.parent		= &ck_ref,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
	.enable_reg	= ARM_IDLECT2,
	.enable_bit	= EN_XORPCK,
	.recalc		= &followparent_recalc,
};

static struct clk armtim_ck = {
	.name		= "armtim_ck",
	.parent		= &ck_ref,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
	.enable_reg	= ARM_IDLECT2,
	.enable_bit	= EN_TIMCK,
	.recalc		= &followparent_recalc,
};

static struct clk armwdt_ck = {
	.name		= "armwdt_ck",
	.parent		= &ck_ref,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
	.enable_reg	= ARM_IDLECT2,
	.enable_bit	= EN_WDTCK,
	.recalc		= &watchdog_recalc,
};

static struct clk arminth_ck16xx = {
	.name		= "arminth_ck",
	.parent		= &arm_ck,
	.flags		= CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
	.recalc		= &followparent_recalc,
	/* Note: On 16xx the frequency can be divided by 2 by programming
	 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
	 *
	 * 1510 version is in TC clocks.
	 */
};

static struct clk dsp_ck = {
	.name		= "dsp_ck",
	.parent		= &ck_dpll1,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
			  RATE_CKCTL,
	.enable_reg	= ARM_CKCTL,
	.enable_bit	= EN_DSPCK,
	.rate_offset	= CKCTL_DSPDIV_OFFSET,
	.recalc		= &ckctl_recalc,
};

static struct clk dspmmu_ck = {
	.name		= "dspmmu_ck",
	.parent		= &ck_dpll1,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
			  RATE_CKCTL | ALWAYS_ENABLED,
	.rate_offset	= CKCTL_DSPMMUDIV_OFFSET,
	.recalc		= &ckctl_recalc,
};

static struct clk dspper_ck = {
	.name		= "dspper_ck",
	.parent		= &ck_dpll1,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
			  RATE_CKCTL | DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
	.enable_reg	= DSP_IDLECT2,
	.enable_bit	= EN_PERCK,
	.rate_offset	= CKCTL_PERDIV_OFFSET,
	.recalc		= &followparent_recalc,
	//.recalc		= &ckctl_recalc,
};

static struct clk dspxor_ck = {
	.name		= "dspxor_ck",
	.parent		= &ck_ref,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
			  DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
	.enable_reg	= DSP_IDLECT2,
	.enable_bit	= EN_XORPCK,
	.recalc		= &followparent_recalc,
};

static struct clk dsptim_ck = {
	.name		= "dsptim_ck",
	.parent		= &ck_ref,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
			  DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
	.enable_reg	= DSP_IDLECT2,
	.enable_bit	= EN_DSPTIMCK,
	.recalc		= &followparent_recalc,
};

static struct clk tc_ck = {
	.name		= "tc_ck",
	.parent		= &ck_dpll1,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 |
			  RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
	.rate_offset	= CKCTL_TCDIV_OFFSET,
	.recalc		= &ckctl_recalc,
};

static struct clk arminth_ck1510 = {
	.name		= "arminth_ck",
	.parent		= &tc_ck,
	.flags		= CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
	.recalc		= &followparent_recalc,
	/* Note: On 1510 the frequency follows TC_CK
	 *
	 * 16xx version is in MPU clocks.
	 */
};

static struct clk tipb_ck = {
	.name		= "tibp_ck",
	.parent		= &tc_ck,
	.flags		= CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
	.recalc		= &followparent_recalc,
};

static struct clk l3_ocpi_ck = {
	.name		= "l3_ocpi_ck",
	.parent		= &tc_ck,
	.flags		= CLOCK_IN_OMAP16XX,
	.enable_reg	= ARM_IDLECT3,
	.enable_bit	= EN_OCPI_CK,
	.recalc		= &followparent_recalc,
};

static struct clk tc1_ck = {
	.name		= "tc1_ck",
	.parent		= &tc_ck,
	.flags		= CLOCK_IN_OMAP16XX,
	.enable_reg	= ARM_IDLECT3,
	.enable_bit	= EN_TC1_CK,
	.recalc		= &followparent_recalc,
};

static struct clk tc2_ck = {
	.name		= "tc2_ck",
	.parent		= &tc_ck,
	.flags		= CLOCK_IN_OMAP16XX,
	.enable_reg	= ARM_IDLECT3,
	.enable_bit	= EN_TC2_CK,
	.recalc		= &followparent_recalc,
};

static struct clk dma_ck = {
	.name		= "dma_ck",
	.parent		= &tc_ck,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
			  ALWAYS_ENABLED,
	.recalc		= &followparent_recalc,
};

static struct clk dma_lcdfree_ck = {
	.name		= "dma_lcdfree_ck",
	.parent		= &tc_ck,
	.flags		= CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
	.recalc		= &followparent_recalc,
};

static struct clk api_ck = {
	.name		= "api_ck",
	.parent		= &tc_ck,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
	.enable_reg	= ARM_IDLECT2,
	.enable_bit	= EN_APICK,
	.recalc		= &followparent_recalc,
};

static struct clk lb_ck = {
	.name		= "lb_ck",
	.parent		= &tc_ck,
	.flags		= CLOCK_IN_OMAP1510,
	.enable_reg	= ARM_IDLECT2,
	.enable_bit	= EN_LBCK,
	.recalc		= &followparent_recalc,
};

static struct clk rhea1_ck = {
	.name		= "rhea1_ck",
	.parent		= &tc_ck,
	.flags		= CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
	.recalc		= &followparent_recalc,
};

static struct clk rhea2_ck = {
	.name		= "rhea2_ck",
	.parent		= &tc_ck,
	.flags		= CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
	.recalc		= &followparent_recalc,
};

static struct clk lcd_ck = {
	.name		= "lcd_ck",
	.parent		= &ck_dpll1,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 |
			  RATE_CKCTL,
	.enable_reg	= ARM_IDLECT2,
	.enable_bit	= EN_LCDCK,
	.rate_offset	= CKCTL_LCDDIV_OFFSET,
	.recalc		= &ckctl_recalc,
};

static struct clk uart1_1510 = {
	.name		= "uart1_ck",
	/* Direct from ULPD, no parent */
	.rate		= 12000000,
	.flags		= CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | ALWAYS_ENABLED,
	.enable_reg	= MOD_CONF_CTRL_0,
	.enable_bit	= 29,	/* Chooses between 12MHz and 48MHz */
	.set_rate	= &set_uart_rate,
	.recalc		= &uart_recalc,
};

static struct clk uart1_16xx = {
	.name		= "uart1_ck",
	/* Direct from ULPD, no parent */
	.rate		= 48000000,
	.flags		= CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT,
	.enable_reg	= MOD_CONF_CTRL_0,
	.enable_bit	= 29,
};

static struct clk uart2_ck = {
	.name		= "uart2_ck",
	/* Direct from ULPD, no parent */
	.rate		= 12000000,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT |
			  ALWAYS_ENABLED,
	.enable_reg	= MOD_CONF_CTRL_0,
	.enable_bit	= 30,	/* Chooses between 12MHz and 48MHz */
	.set_rate	= &set_uart_rate,
	.recalc		= &uart_recalc,
};

static struct clk uart3_1510 = {
	.name		= "uart3_ck",
	/* Direct from ULPD, no parent */
	.rate		= 12000000,
	.flags		= CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | ALWAYS_ENABLED,
	.enable_reg	= MOD_CONF_CTRL_0,
	.enable_bit	= 31,	/* Chooses between 12MHz and 48MHz */
	.set_rate	= &set_uart_rate,
	.recalc		= &uart_recalc,
};

static struct clk uart3_16xx = {
	.name		= "uart3_ck",
	/* Direct from ULPD, no parent */
	.rate		= 48000000,
	.flags		= CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT,
	.enable_reg	= MOD_CONF_CTRL_0,
	.enable_bit	= 31,
};

static struct clk usb_clko = {	/* 6 MHz output on W4_USB_CLKO */
	.name		= "usb_clko",
	/* Direct from ULPD, no parent */
	.rate		= 6000000,
	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
			  RATE_FIXED | ENABLE_REG_32BIT,
	.enable_reg	= ULPD_CLOCK_CTRL,
	.enable_bit	= USB_MCLK_EN_BIT,
};

static struct clk usb_hhc_ck1510 = {
	.name		= "usb_hhc_ck",
	/* Direct from ULPD, no parent */
	.rate		= 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
	.flags		= CLOCK_IN_OMAP1510 |
			  RATE_FIXED | ENABLE_REG_32BIT,
	.enable_reg	= MOD_CONF_CTRL_0,
	.enable_bit	= USB_HOST_HHC_UHOST_EN,
};

static struct clk usb_hhc_ck16xx = {
	.name		= "usb_hhc_ck",
	/* Direct from ULPD, no parent */
	.rate		= 48000000,
	/* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
	.flags		= CLOCK_IN_OMAP16XX |
			  RATE_FIXED | ENABLE_REG_32BIT,
	.enable_reg	= OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
	.enable_bit	= 8 /* UHOST_EN */,
};