head.s

底层驱动开发

	LEDS		0x3505
	call		__head_fr555_set_protection

__head_done_memmap:
#endif
	LEDS		0x0007

###############################################################################
#
# turn the data cache and MMU on
# - for the FR451 this'll mean that the window through which the kernel is
#   viewed will change
#
###############################################################################

#ifdef CONFIG_MMU
#define MMUMODE		HSR0_EIMMU|HSR0_EDMMU|HSR0_EXMMU|HSR0_EDAT|HSR0_XEDAT
#else
#define MMUMODE		HSR0_EIMMU|HSR0_EDMMU
#endif

	movsg		hsr0,gr5

	sethi.p		%hi(MMUMODE),gr4
	setlo		%lo(MMUMODE),gr4
	or		gr4,gr5,gr5

#if defined(CONFIG_FRV_DEFL_CACHE_WTHRU)
	sethi.p		%hi(HSR0_DCE|HSR0_CBM_WRITE_THRU),gr4
	setlo		%lo(HSR0_DCE|HSR0_CBM_WRITE_THRU),gr4
#elif defined(CONFIG_FRV_DEFL_CACHE_WBACK)
	sethi.p		%hi(HSR0_DCE|HSR0_CBM_COPY_BACK),gr4
	setlo		%lo(HSR0_DCE|HSR0_CBM_COPY_BACK),gr4
#elif defined(CONFIG_FRV_DEFL_CACHE_WBEHIND)
	sethi.p		%hi(HSR0_DCE|HSR0_CBM_COPY_BACK),gr4
	setlo		%lo(HSR0_DCE|HSR0_CBM_COPY_BACK),gr4

	movsg		psr,gr6
	srli		gr6,#24,gr6
	cmpi		gr6,#0x50,icc0		// FR451
	beq		icc0,#0,0f
	cmpi		gr6,#0x40,icc0		// FR405
	bne		icc0,#0,1f
0:
	# turn off write-allocate
	sethi.p		%hi(HSR0_NWA),gr6
	setlo		%lo(HSR0_NWA),gr6
	or		gr4,gr6,gr4
1:

#else
#error No default cache configuration set
#endif

	or		gr4,gr5,gr5
	movgs		gr5,hsr0
	bar

	LEDS		0x0008

	sethi.p		%hi(__head_mmu_enabled),gr19
	setlo		%lo(__head_mmu_enabled),gr19
	jmpl		@(gr19,gr0)

__head_mmu_enabled:
	icei		@(gr0,gr0),#1
	dcei		@(gr0,gr0),#1

	LEDS		0x0009

#ifdef CONFIG_MMU
	call		__head_fr451_finalise_protection
#endif

	LEDS		0x000a

###############################################################################
#
# set up the runtime environment
#
###############################################################################

	# clear the BSS area
	sethi.p		%hi(__bss_start),gr4
	setlo		%lo(__bss_start),gr4
	sethi.p		%hi(_end),gr5
	setlo		%lo(_end),gr5
	or.p		gr0,gr0,gr18
	or		gr0,gr0,gr19

0:
	stdi		gr18,@(gr4,#0)
	stdi		gr18,@(gr4,#8)
	stdi		gr18,@(gr4,#16)
	stdi.p		gr18,@(gr4,#24)
	addi		gr4,#24,gr4
	subcc		gr5,gr4,gr0,icc0
	bhi		icc0,#2,0b

	LEDS		0x000b

	# save the SDRAM details
	sethi.p		%hi(__sdram_old_base),gr4
	setlo		%lo(__sdram_old_base),gr4
	st		gr24,@(gr4,gr0)

	sethi.p		%hi(__sdram_base),gr5
	setlo		%lo(__sdram_base),gr5
	sethi.p		%hi(memory_start),gr4
	setlo		%lo(memory_start),gr4
	st		gr5,@(gr4,gr0)

	add		gr25,gr5,gr25
	sethi.p		%hi(memory_end),gr4
	setlo		%lo(memory_end),gr4
	st		gr25,@(gr4,gr0)

	# point the TBR at the kernel trap table
	sethi.p		%hi(__entry_kerneltrap_table),gr4
	setlo		%lo(__entry_kerneltrap_table),gr4
	movgs		gr4,tbr

	# set up the exception frame for init
	sethi.p		%hi(__kernel_frame0_ptr),gr28
	setlo		%lo(__kernel_frame0_ptr),gr28
	sethi.p		%hi(_gp),gr16
	setlo		%lo(_gp),gr16
	sethi.p		%hi(__entry_usertrap_table),gr4
	setlo		%lo(__entry_usertrap_table),gr4

	lddi		@(gr28,#0),gr28		; load __frame & current
	ldi.p		@(gr29,#4),gr15		; set current_thread

	or		gr0,gr0,fp
	or		gr28,gr0,sp

	sti.p		gr4,@(gr28,REG_TBR)
	setlos		#ISR_EDE|ISR_DTT_DIVBYZERO|ISR_EMAM_EXCEPTION,gr5
	movgs		gr5,isr

	# turn on and off various CPU services
	movsg		psr,gr22
	sethi.p		%hi(#PSR_EM|PSR_EF|PSR_CM|PSR_NEM),gr4
	setlo		%lo(#PSR_EM|PSR_EF|PSR_CM|PSR_NEM),gr4
	or		gr22,gr4,gr22
	movgs		gr22,psr

	andi		gr22,#~(PSR_PIL|PSR_PS|PSR_S),gr22
	ori		gr22,#PSR_ET,gr22
	sti		gr22,@(gr28,REG_PSR)


###############################################################################
#
# set up the registers and jump into the kernel
#
###############################################################################

	LEDS		0x000c

	# initialise the processor and the peripherals
	#call		SYMBOL_NAME(processor_init)
	#call		SYMBOL_NAME(unit_init)
	#LEDS		0x0aff

	sethi.p		#0xe5e5,gr3
	setlo		#0xe5e5,gr3
	or.p		gr3,gr0,gr4
	or		gr3,gr0,gr5
	or.p		gr3,gr0,gr6
	or		gr3,gr0,gr7
	or.p		gr3,gr0,gr8
	or		gr3,gr0,gr9
	or.p		gr3,gr0,gr10
	or		gr3,gr0,gr11
	or.p		gr3,gr0,gr12
	or		gr3,gr0,gr13
	or.p		gr3,gr0,gr14
	or		gr3,gr0,gr17
	or.p		gr3,gr0,gr18
	or		gr3,gr0,gr19
	or.p		gr3,gr0,gr20
	or		gr3,gr0,gr21
	or.p		gr3,gr0,gr23
	or		gr3,gr0,gr24
	or.p		gr3,gr0,gr25
	or		gr3,gr0,gr26
	or.p		gr3,gr0,gr27
#	or		gr3,gr0,gr30
	or		gr3,gr0,gr31
	movgs		gr0,lr
	movgs		gr0,lcr
	movgs		gr0,ccr
	movgs		gr0,cccr

#ifdef CONFIG_MMU
	movgs		gr3,scr2
	movgs		gr3,scr3
#endif

	LEDS		0x0fff

	# invoke the debugging stub if present
	# - arch/frv/kernel/debug-stub.c will shift control directly to init/main.c
	#   (it will not return here)
	break
	.globl		__debug_stub_init_break
__debug_stub_init_break:

	# however, if you need to use an ICE, and don't care about using any userspace
	# debugging tools (such as the ptrace syscall), you can just step over the break
	# above and get to the kernel this way
	# look at arch/frv/kernel/debug-stub.c: debug_stub_init() to see what you've missed
	call		start_kernel

	.globl		__head_end
__head_end:
	.size		_boot, .-_boot

	# provide a point for GDB to place a break
	.section	.text.start,"ax"
	.globl		_start
	.balign		4
_start:
	call		_boot

	.previous
###############################################################################
#
# split a tile off of the region defined by GR8-GR9
#
#	ENTRY:			EXIT:
# GR4	-			IAMPR value representing tile
# GR5	-			DAMPR value representing tile
# GR6	-			IAMLR value representing tile
# GR7	-			DAMLR value representing tile
# GR8	region base pointer	[saved]
# GR9	region top pointer	updated to exclude new tile
# GR11	xAMLR mask		[saved]
# GR25	SDRAM size		[saved]
# GR30	LED address		[saved]
#
# - GR8 and GR9 should be rounded up/down to the nearest megabyte before calling
#
###############################################################################
	.globl		__head_split_region
	.type		__head_split_region,@function
__head_split_region:
	subcc.p		gr9,gr8,gr4,icc0
	setlos		#31,gr5
	scan.p		gr4,gr0,gr6
	beq		icc0,#0,__head_region_empty
	sub.p		gr5,gr6,gr6			; bit number of highest set bit (1MB=>20)
	setlos		#1,gr4
	sll.p		gr4,gr6,gr4			; size of region (1 << bitno)
	subi		gr6,#17,gr6			; 1MB => 0x03
	slli.p		gr6,#4,gr6			; 1MB => 0x30
	sub		gr9,gr4,gr9			; move uncovered top down

	or		gr9,gr6,gr4
	ori		gr4,#xAMPRx_S_USER|xAMPRx_C_CACHED|xAMPRx_V,gr4
	or.p		gr4,gr0,gr5

	and		gr4,gr11,gr6
	and.p		gr5,gr11,gr7
	bralr

__head_region_empty:
	or.p		gr0,gr0,gr4
	or		gr0,gr0,gr5
	or.p		gr0,gr0,gr6
	or		gr0,gr0,gr7
	bralr
	.size		__head_split_region, .-__head_split_region

###############################################################################
#
# write the 32-bit hex number in GR8 to ttyS0
#
###############################################################################
#if 0
	.globl		__head_write_to_ttyS0
	.type		__head_write_to_ttyS0,@function
__head_write_to_ttyS0:
	sethi.p		%hi(0xfeff9c00),gr31
	setlo		%lo(0xfeff9c00),gr31
	setlos		#8,gr20

0:	ldubi		@(gr31,#5*8),gr21
	andi		gr21,#0x60,gr21
	subicc		gr21,#0x60,gr21,icc0
	bne		icc0,#0,0b

1:	srli		gr8,#28,gr21
	slli		gr8,#4,gr8

	addi		gr21,#'0',gr21
	subicc		gr21,#'9',gr0,icc0
	bls		icc0,#2,2f
	addi		gr21,#'A'-'0'-10,gr21
2:
	stbi		gr21,@(gr31,#0*8)
	subicc		gr20,#1,gr20,icc0
	bhi		icc0,#2,1b

	setlos		#'\r',gr21
	stbi		gr21,@(gr31,#0*8)

	setlos		#'\n',gr21
	stbi		gr21,@(gr31,#0*8)

3:	ldubi		@(gr31,#5*8),gr21
	andi		gr21,#0x60,gr21
	subicc		gr21,#0x60,gr21,icc0
	bne		icc0,#0,3b
	bralr

	.size		__head_write_to_ttyS0, .-__head_write_to_ttyS0
#endif