hostmot2.vhd

CNC 的开放码,EMC2 V2.2.8版

				fpgapins => FPGAPins,
				ioports => IOPorts,
				iowidth => IOWidth,
				portwidth => PortWidth,		
				clocklow => ClockLow,
				clockhigh => ClockHigh,
				inststride0 => InstStride0,
				inststride1 => InstStride1,
				regstride0 => RegStride0,
				regstride1 => RegStride1,
				pindesc => PinDesc_4xi30,
				moduleid => ModuleID_4xi30)
			port map (
				clk  => clklow, 
				we   => LoadIDROM,
				re   => ReadIDROM,
				radd => addr(9 downto 2),
				wadd => A(9 downto 2),
				din  => ibus, 
				dout => obus
		); 
	end generate;
		
	SVST8_4s: if  SVST8_4Pinout generate
		IDROM : entity IDROM
			generic map (
				idromtype => IDROMType,
				offsettomodules => OffsetToModules,
				offsettopindesc => OffsetToPinDesc,
				boardnamelow => BoardNameLow,
				boardnamehigh => BoardNameHigh,
				fpgasize => FPGASize,
				fpgapins => FPGAPins,
				ioports => IOPorts,
				iowidth => IOWidth,
				portwidth => PortWidth,		
				clocklow => ClockLow,
				clockhigh => ClockHigh,
				inststride0 => InstStride0,
				inststride1 => InstStride1,
				regstride0 => RegStride0,
				regstride1 => RegStride1,
				pindesc => PinDesc_SVST8_4,
				moduleid => ModuleID_SVST8_4)
			port map (
				clk  => clklow, 
				we   => LoadIDROM,
				re   => ReadIDROM,
				radd => addr(9 downto 2),
				wadd => A(9 downto 2),
				din  => ibus, 
				dout => obus
		); 
	end generate;
	
	SVST4_8s: if  SVST4_8Pinout generate
		IDROM : entity IDROM
			generic map (
				idromtype => IDROMType,
				offsettomodules => OffsetToModules,
				offsettopindesc => OffsetToPinDesc,
				boardnamelow => BoardNameLow,
				boardnamehigh => BoardNameHigh,
				fpgasize => FPGASize,
				fpgapins => FPGAPins,
				ioports => IOPorts,
				iowidth => IOWidth,
				portwidth => PortWidth,		
				clocklow => ClockLow,
				clockhigh => ClockHigh,
				inststride0 => InstStride0,
				inststride1 => InstStride1,
				regstride0 => RegStride0,
				regstride1 => RegStride1,
				pindesc => PinDesc_SVST4_8,
				moduleid => ModuleID_SVST4_8)
			port map (
				clk  => clklow, 
				we   => LoadIDROM,
				re   => ReadIDROM,
				radd => addr(9 downto 2),
				wadd => A(9 downto 2),
				din  => ibus, 
				dout => obus
		); 
	end generate;

	SVST8_8s: if  SVST8_8Pinout generate
		IDROM : entity IDROM
			generic map (
				idromtype => IDROMType,
				offsettomodules => OffsetToModules,
				offsettopindesc => OffsetToPinDesc,
				boardnamelow => BoardNameLow,
				boardnamehigh => BoardNameHigh,
				fpgasize => FPGASize,
				fpgapins => FPGAPins,
				ioports => IOPorts,
				iowidth => IOWidth,
				portwidth => PortWidth,		
				clocklow => ClockLow,
				clockhigh => ClockHigh,
				inststride0 => InstStride0,
				inststride1 => InstStride1,
				regstride0 => RegStride0,
				regstride1 => RegStride1,
				pindesc => PinDesc_SVST8_8,
				moduleid => ModuleID_SVST8_8)
			port map (
				clk  => clklow, 
				we   => LoadIDROM,
				re   => ReadIDROM,
				radd => addr(9 downto 2),
				wadd => A(9 downto 2),
				din  => ibus, 
				dout => obus
		); 
	end generate;	

	SVST8_24s: if  SVST8_24Pinout generate
		IDROM : entity IDROM
			generic map (
				idromtype => IDROMType,
				offsettomodules => OffsetToModules,
				offsettopindesc => OffsetToPinDesc,
				boardnamelow => BoardNameLow,
				boardnamehigh => BoardNameHigh,
				fpgasize => FPGASize,
				fpgapins => FPGAPins,
				ioports => IOPorts,
				iowidth => IOWidth,
				portwidth => PortWidth,		
				clocklow => ClockLow,
				clockhigh => ClockHigh,
				inststride0 => InstStride0,
				inststride1 => InstStride1,
				regstride0 => RegStride0,
				regstride1 => RegStride1,
				pindesc => PinDesc_SVST8_24,
				moduleid => ModuleID_SVST8_24)
			port map (
				clk  => clklow, 
				we   => LoadIDROM,
				re   => ReadIDROM,
				radd => addr(9 downto 2),
				wadd => A(9 downto 2),
				din  => ibus, 
				dout => obus
		); 
	end generate;	

	SVST4_4s: if  SVST4_4Pinout generate
		IDROM : entity IDROM
			generic map (
				idromtype => IDROMType,
				offsettomodules => OffsetToModules,
				offsettopindesc => OffsetToPinDesc,
				boardnamelow => BoardNameLow,
				boardnamehigh => BoardNameHigh,
				fpgasize => FPGASize,
				fpgapins => FPGAPins,
				ioports => IOPorts,
				iowidth => IOWidth,
				portwidth => PortWidth,		
				clocklow => ClockLow,
				clockhigh => ClockHigh,
				inststride0 => InstStride0,
				inststride1 => InstStride1,
				regstride0 => RegStride0,
				regstride1 => RegStride1,
				pindesc => PinDesc_SVST4_4,
				moduleid => ModuleID_SVST4_4)
			port map (
				clk  => clklow, 
				we   => LoadIDROM,
				re   => ReadIDROM,
				radd => addr(9 downto 2),
				wadd => A(9 downto 2),
				din  => ibus, 
				dout => obus
		); 
	end generate;	

	SVST4_6s: if  SVST4_6Pinout generate
		IDROM : entity IDROM
			generic map (
				idromtype => IDROMType,
				offsettomodules => OffsetToModules,
				offsettopindesc => OffsetToPinDesc,
				boardnamelow => BoardNameLow,
				boardnamehigh => BoardNameHigh,
				fpgasize => FPGASize,
				fpgapins => FPGAPins,
				ioports => IOPorts,
				iowidth => IOWidth,
				portwidth => PortWidth,		
				clocklow => ClockLow,
				clockhigh => ClockHigh,
				inststride0 => InstStride0,
				inststride1 => InstStride1,
				regstride0 => RegStride0,
				regstride1 => RegStride1,
				pindesc => PinDesc_SVST4_6,
				moduleid => ModuleID_SVST4_6)
			port map (
				clk  => clklow, 
				we   => LoadIDROM,
				re   => ReadIDROM,
				radd => addr(9 downto 2),
				wadd => A(9 downto 2),
				din  => ibus, 
				dout => obus
		); 
	end generate;	
		
		IDROM_24X_QCtrsOnly: if QCtrOnlyPinout and (QCOUNTERS = 24) generate
		IDROM : entity IDROM
			generic map (
				idromtype => IDROMType,
				offsettomodules => OffsetToModules,
				offsettopindesc => OffsetToPinDesc,
				boardnamelow => BoardNameLow,
				boardnameHigh => BoardNameHigh,
				fpgasize => FPGASize,
				fpgapins => FPGAPins,
				ioports => IOPorts,
				iowidth => IOWidth,
				portwidth => PortWidth,		
				clocklow => ClockLow,
				clockhigh => ClockHigh,
				inststride0 => InstStride0,
				inststride1 => InstStride1,
				regstride0 => RegStride0,
				regstride1 => RegStride1,
				pindesc => PinDesc_24xQCtrOnly,
				moduleid => ModuleID_24xQCtrOnly)
			port map (
				clk  => clklow, 
				we   => LoadIDROM,
				re   => ReadIDROM,
				radd => addr(9 downto 2),
				wadd => A(9 downto 2),
				din  => ibus, 
				dout => obus
		); 
	end generate;
	   
	
		doi3xpinout: if I30Pinout generate
			ConnectAltFuncs3X: process(PWMGenoutA,PWMGenOutB,
											QuadA,QuadB,Index,IndexMask,IOBits,PWMGenOutC)
			begin
--				Altdata <= (others => '0');
					
					for i in StartingI30Conn to StartingI30Conn + ConnsWithI30 -1 loop
					-- Note for 7I29/7I30/7I33/7I40  -- PWMGenOutA = PWM, PWMGenOutB = DIR, PWMGenOutC = ENA
					QuadB(4*i+1) <= IOBits(PortWidth*i+0);
					QuadA(4*i+1) <= IOBits(PortWidth*i+1);
					QuadB(4*i+0) <= IOBits(PortWidth*i+2);
					QuadA(4*i+0) <= IOBits(PortWidth*i+3);
					Index(4*i+1) <= IOBits(PortWidth*i+4);
					Index(4*i+0) <= IOBits(PortWidth*i+5);
					AltData(PortWidth*i+6) <= PWMGenOutA(4*i+1);					
					AltData(PortWidth*i+7) <= PWMGenOutA(4*i+0);
					AltData(PortWidth*i+8) <= PWMGenOutB(4*i+1);					
					AltData(PortWidth*i+9) <= PWMGenOutB(4*i+0);					
					AltData(PortWidth*i+10) <= not PWMGenOutC(4*i+1);					
					AltData(PortWidth*i+11) <= not PWMGenOutC(4*i+0);				
					QuadB(4*i+3) <= IOBits(PortWidth*i+12);					
					QuadA(4*i+3) <= IOBits(PortWidth*i+13);					
					QuadB(4*i+2) <= IOBits(PortWidth*i+14);				
					QuadA(4*i+2) <= IOBits(PortWidth*i+15);
					Index(4*i+3) <= IOBits(PortWidth*i+16);
					Index(4*i+2) <= IOBits(PortWidth*i+17);
					AltData(PortWidth*i+18) <= PWMGenOutA(4*i+3);					
					AltData(PortWidth*i+19) <= PWMGenOutA(4*i+2);					
					AltData(PortWidth*i+20) <= PWMGenOutB(4*i+3);					
					AltData(PortWidth*i+21) <= PWMGenOutB(4*i+2);
					AltData(PortWidth*i+22) <= not PWMGenOutC(4*i+3);
					AltData(PortWidth*i+23) <= not PWMGenOutC(4*i+2);
				
				end loop;

			end process;
		end generate;


	

		doi44pinout: if I44Pinout generate
			ConnectAltFuncs44: process(UTXData,UTRData)
			begin
				Altdata <= (others => '0');
				for i in 0 to ConnsWithI44 -1 loop
					-- Note -- for 7I44  
					UTRdata(8*i +0) <= IOBits(PortWidth*i+0);	
					UTRdata(8*i +1) <= IOBits(PortWidth*i+1);
					UTRdata(8*i +2) <= IOBits(PortWidth*i+2);
					UTRdata(8*i +3) <= IOBits(PortWidth*i+3);
					AltData(PortWidth*i+4) <= UTXData(8*i +0);
					AltData(PortWidth*i+5) <= UTDrvEn(8*i +0);					
					AltData(PortWidth*i+6) <= UTXData(8*i +1);
					AltData(PortWidth*i+7) <= UTDrvEn(8*i +1);					
					AltData(PortWidth*i+8) <= UTXData(8*i +2);
					AltData(PortWidth*i+9) <= UTDrvEn(8*i +2);					
					AltData(PortWidth*i+10) <= UTXData(8*i +3);
					AltData(PortWidth*i+11) <= UTDrvEn(8*i +3);
					UTRdata(8*i +4) <= IOBits(PortWidth*i+12);
					UTRdata(8*i +5) <= IOBits(PortWidth*i+13);
					UTRdata(8*i +6) <= IOBits(PortWidth*i+14);
					UTRdata(8*i +7) <= IOBits(PortWidth*i+15);
					AltData(PortWidth*i+16) <= UTXData(8*i +4);
					AltData(PortWidth*i+17) <= UTDrvEn(8*i +4);					
					AltData(PortWidth*i+18) <= UTXData(8*i +5);
					AltData(PortWidth*i+19) <= UTDrvEn(8*i +5);					
					AltData(PortWidth*i+20) <= UTXData(8*i +6);
					AltData(PortWidth*i+21) <= UTDrvEn(8*i +6);					
					AltData(PortWidth*i+22) <= UTXData(8*i +7);
					AltData(PortWidth*i+23) <= UTDrvEn(8*i +7);					
				end loop;
			end process;
		end generate;
		

				
		QctrOnlypinoutWithImaskGen: if QCtrOnlyPinoutWithIMask generate
			ConnectAltFuncsQC: process(QuadA,QuadB,Index,IndexMask)
			begin	
				for i in 0 to Qcounters-1 loop
					QuadA(i)     <= IOBits(4*i+0);				
					QuadB(i)     <= IOBits(4*i+1);
					Index(i)     <= IOBits(4*i+2);					
					IndexMask(i) <= IOBits(4*i+3);
				end loop;	
			end process;		
		end generate;	

		QctrOnlypinoutGen: if QCtrOnlyPinout generate
			ConnectAltFuncsQC: process(QuadA,QuadB,Index)
			begin	
				for i in 0 to Qcounters-1 loop
					QuadA(i)     <= IOBits(3*i+0);				
					QuadB(i)     <= IOBits(3*i+1);
					Index(i)     <= IOBits(3*i+2);						
				end loop;		
			end process;		
		end generate;	


		SVSTStepGens: if StepGens > 0  generate
			ConnectAltFuncsQC: process(StepGenOut)
			begin	
				for i in 0 to StepGens-1 loop
					for j in 0 to StepGenTableWidth-1 loop
						AltData(StepGenTableWidth*i+PortWidth*StartingStepGenConn+j) <= StepGenOut(i)(j);				
					end loop;
				end loop;	
			end process;		
		end generate;	

   LooseEnds: process(A,clklow)
	begin
		if rising_edge(clklow) then
			A <= addr;
		end if;
	end process;



	Decode: process(A,write, IDROMWEn, read) 
	begin	
		-- basic multi decodes are at 256 byte increments (64 longs)
		-- first decode is 256 x 32 ID ROM


		if (A(15 downto 10) = IDROMAddr(7 downto 2)) and Write = '1' and IDROMWEn = "1" then	 -- 400 Hex  
			LoadIDROM <= '1';
		else
			LoadIDROM <= '0';
		end if;
		if (A(15 downto 10) = IDROMAddr(7 downto 2)) and Read = '1' then	 --  
			ReadIDROM <= '1';
		else
			ReadIDROM <= '0';
		end if;

		if A(15 downto 8) = PortAddr then  -- basic I/O port select
			PortSel <= '1';
		else
			PortSel <= '0';
		end if;

		if A(15 downto 8) = DDRAddr then	 -- DDR register select
			DDRSel <= '1';
		else
			DDRSel <= '0';
		end if;

		if A(15 downto 8) = AltDataSrcAddr then  -- Alt data source register select
			AltDataSrcSel <= '1';
		else
			AltDataSrcSel <= '0';
		end if;