hostmot2.vhd

CNC 的开放码,EMC2 V2.2.8版

	makeiports: for i in 0 to IOPorts -1 generate
		iportx: entity WordRB 		  
		generic map (size => PortWidth,
						 buswidth => BusWidth)
		port map (
		obus => obus,
		readport => ReadPortCmd(i),
		portdata => IOBits((((i+1)*PortWidth) -1) downto (i*PortWidth))
 		);	
	end generate;

	makewatchdog: if UseWatchDog generate  
		wdogabittus: entity watchdog
		generic map ( buswidth => BusWidth)
		
		port map (
			clk => clklow,
			ibus => ibus,
			obus => obus,
			loadtime => LoadWDTime, 
			readtime => ReadWDTime,
			loadstatus=> LoadWDStatus,
			readstatus=> ReadWDStatus,
			cookie => WDCookie,
			wdbite => WDBite,
			wdlatchedbite => WDLatchedBite
			);
		end generate;

	makeirqlogic: if UseIRQlogic generate
		somoldirqlogic: entity irqlogic    
		generic map( 
			buswidth =>  BusWidth,
			dividerwidth => 16
				)	
		port map ( 
			clk => clklow,
			ibus => ibus,
         obus =>  obus,
         loaddiv => LoadIRQDiv,
         readdiv => ReadIRQDiv,
         loadstatus => LoadIRQStatus,
         readstatus => ReadIrqStatus,
         clear =>  ClearIRQ,
         ratesource => RefCountBus(PWMRefWidth-1 downto PWMRefWidth-8), -- from toggle bit all the way to 8X PWM rate
         int => INT);
	end generate;
	
	makeStepGenPreScaler:  if UseStepGenPreScaler generate
		StepRategen : entity RateGen port map(
		 	ibus => ibus,
  		   obus => obus,
      	loadbasicrate => LoadStepGenBasicRate,
      	readbasicrate => ReadStepGenBasicRate,
			hold => '0',
      	basicrate => StepGenBasicRate,
      	clk => clklow);
		end generate;

	makestepgens: for i in 0 to StepGens-1 generate
		usg: if UseStepGenPreScaler generate
		stepgenx: entity stepgen
		generic map (
			buswidth => BusWidth,
			timersize => 14,			-- = ~480 usec at 33 MHz, ~320 at 50 Mhz 
			tablewidth => StepGenTableWidth,
			asize => 48,
			rsize => 32 
			)
		port map (
			clk => clklow,
			ibus => ibus,
			obus 	=>	 obus,
			loadsteprate => LoadStepGenRate(i),
			loadaccum => LoadStepGenAccum(i),
			loadstepmode => LoadStepGenMode(i),
			loaddirsetuptime => LoadStepGenDSUTime(i),
			loaddirholdtime => LoadStepGenDHLDTime(i),
			loadpulseactivetime => LoadStepGenPulseATime(i),
			loadpulseidletime => LoadStepGenPulseITime(i),
			loadtable => LoadStepGenTable(i),
			loadtablemax => LoadStepGenTableMax(i),
 			readsteprate => ReadStepGenRate(i),
			readaccum => ReadStepGenAccum(i),
			readstepmode => ReadStepGenMode(i),
			readdirsetuptime => ReadStepGenDSUTime(i),
			readdirholdtime => ReadStepGenDHLDTime(i),
			readpulseactivetime => ReadStepGenPulseATime(i),
			readpulseidletime => ReadStepGenPulseITime(i),
			readtable => ReadStepGenTable(i),
			readtablemax => ReadStepGenTableMax(i),
			basicrate => StepGenBasicRate,
			hold => '0',
			stout => StepGenOut(i)
          );
		end generate usg;
		
		nusg: if not UseStepGenPreScaler generate
		stepgenx: entity stepgen
		generic map (
			buswidth => BusWidth,
			timersize => 14,			-- = ~480 usec at 33 MHz, ~320 at 50 Mhz 
			tablewidth => StepGenTableWidth,
			asize => 48,
			rsize => 32 			
			)
		port map (
			clk => clklow,
			ibus => ibus,
			obus 	=>	 obus,
			loadsteprate => LoadStepGenRate(i),
			loadaccum => LoadStepGenAccum(i),
			loadstepmode => LoadStepGenMode(i),
			loaddirsetuptime => LoadStepGenDSUTime(i),
			loaddirholdtime => LoadStepGenDHLDTime(i),
			loadpulseactivetime => LoadStepGenPulseATime(i),
			loadpulseidletime => LoadStepGenPulseITime(i),
			loadtable => LoadStepGenTable(i),
			loadtablemax => LoadStepGenTableMax(i),
 			readsteprate => ReadStepGenRate(i),
			readaccum => ReadStepGenAccum(i),
			readstepmode => ReadStepGenMode(i),
			readdirsetuptime => ReadStepGenDSUTime(i),
			readdirholdtime => ReadStepGenDHLDTime(i),
			readpulseactivetime => ReadStepGenPulseATime(i),
			readpulseidletime => ReadStepGenPulseITime(i),
			readtable => ReadStepGenTable(i),
			readtablemax => ReadStepGenTableMax(i),
			basicrate => '1',
			hold => '0',
			stout => StepGenOut(i)  -- densely packed starting with I/O bit 0
         );
		end generate nusg;

	end generate makestepgens;

	makequadcounters: for i in 0 to QCounters-1 generate
		qcounterx: entity qcounter 
		generic map (
			buswidth => BusWidth
		)
		port map (
			obus => obus,
			ibus => ibus,
			quada => QuadA(i),
			quadb => QuadB(i),
			index => Index(i),
			loadccr => LoadQcounterCCR(i),
			readccr => ReadQcounterCCR(i),
			readcount => ReadQcounter(i),
			countclear => LoadQcounter(i),
			timestamp => TimeStampBus,
			indexmask => IndexMask(i),
			filterrate => QCountFilterRate,
			clk =>	clklow
		);
	end generate makequadcounters;

	maketqcounterglobals:  if (QCounters >0) generate
		timestampx: entity timestamp 
			port map( 
				ibus => ibus(15 downto 0),
				obus => obus(15 downto 0),
				loadtsdiv => LoadTSDiv ,
				readts => ReadTS,
				readtsdiv =>ReadTSDiv,
				tscount => TimeStampBus,
				clk => clklow
			);
				
			qcountratex: entity qcounterate 
			port map( 
				ibus => ibus(11 downto 0),
				loadRate => LoadQCountRate,
				rateout => QcountFilterRate,
				clk => clklow
			);
	end generate;
		
		
	makepwmref:  if ((PWMGens > 0) or UseIRQLogic) generate
		pwmref : entity pwmrefh
		generic map ( 
			buswidth => 16,
			refwidth => PWMRefWidth			-- Normally 13	for 12,11,10, and 9 bit PWM resolutions = 25KHz,50KHz,100KHz,200KHz max. Freq
			)
		port map (
			clk => clklow,
			hclk => clkhigh,
			refcount	=> RefCountBus,
			ibus => ibus(15 downto 0),
			pdmrate => PDMRate,
			pwmrateload => LoadPWMRate,
			pdmrateload => LoadPDMRate
			);	
	end generate;
	
	makepwmgens : for i in 0 to PWMGens-1 generate
		pwmgenx: entity pwmpdmgenh
		generic map ( 
			buswidth => BusWidth,
			refwidth => PWMRefWidth			-- Normally 13 for 12,11,10, and 9 bit PWM resolutions = 25KHz,50KHz,100KHz,200KHz max. Freq
			)
		port map (
			clk => clklow,
			hclk => clkhigh,
			refcount	=> RefCountBus,
			ibus => ibus,
			loadpwmval => LoadPWMVal(i),
			pcrloadcmd => LoadPWMCR(i),
			pdmrate => PDMRate,
			pwmouta => PWMGenOutA(i),
			pwmoutb => PWMGenOutB(i)
		 	);
	end generate;

	makePWMEna:  if (PWMGens >0) generate
		PWMEnaReg : entity boutreg 
			generic map (
				size => PWMGens,
				buswidth => BusWidth,
				invert => false
				)
			port map (
				clk  => clklow,
				ibus => ibus,
				obus => obus,
				load => LoadPWMEnas,
				read => ReadPWMEnas,
				clear => '0',
				dout => PWMGenOutC
		); 
		 		
	end generate;
	
	makeSPIs: for i in 0 to SPIs -1 generate
		aspi: entity SimpleSPI
		generic map (
			buswidth => BusWidth)		
		port map (
			clk  => clklow,
			ibus => ibus,
			obus => obus,
			loadbitcount => LoadSPIBitCount(i),
			loadbitrate => LoadSPIBitRate(i),
			loaddata => LoadSPIData(i),
			readdata => ReadSPIData(i),           
			readbitcount => ReadSPIBitCOunt(i),
			readbitrate => ReadSPIBitRate(i),
			spiclk => SPIClk(i),
			spiin => SPIIn(i),
			spiout => SPIOut(i),
			spiframe => SPIFrame(i),
			davout => SPIDAV(i)
			);
	end generate;	

	makeUARTRs: for i in 0 to UARTs -1 generate
		auarrx: entity uartr	
		port map (
			clk => clklow,
			ibus => ibus,
			obus => obus,
			addr => A(3 downto 2),
			popfifo => LoadUARTRData(i),
			loadbitrate => LoadUARTRBitRate(i),
			readbitrate => ReadUARTRBitrate(i),
			clrfifo => ClearUARTRFIFO(i),
			readfifocount => ReadUARTRFIFOCount(i),
			loadmode => LoadUARTRMode(i),
			readmode => ReadUARTRMode(i),
			fifohasdata => UARTRFIFOHasData(i),
			rxmask => UTDrvEn(i),			-- for half duplex rx mask
			rxdata => UTRData(i)
         );
	end generate;
	
	makeUARTTXs: for i in 0 to UARTs -1 generate
		auartx:  entity uartx	
		port map (
			clk => clklow,
			ibus => ibus,
			obus => obus,
			addr => A(3 downto 2),
			pushfifo => LoadUARTXData(i),
			loadbitrate => LoadUARTXBitRate(i),
			readbitrate => ReadUARTXBitrate(i),
			clrfifo => ClearUARTXFIFO(i),
			readfifocount => ReadUARTXFIFOCount(i),
			loadmode => LoadUARTXModeReg(i),
			readmode => ReadUARTXModeReg(i),
			fifoempty => UARTXFIFOEmpty(i),
			txen => '1',
			drven => UTDrvEn(i),
			txdata => UTXData(i)
         );
	end generate;

	LEDReg : entity boutreg 
	generic map (
		size => LEDCount,
		buswidth => LEDCount,
		invert => true)
	port map (
		clk  => clklow,
		ibus => ibus(BusWidth-1 downto BusWidth-LEDCount),
		obus => obus(BusWidth-1 downto BusWidth-LEDCount),
		load => LoadLEDs,
		read => '0',
		clear => '0',
		dout => LEDS
		); 

		
	IDROMWP : entity boutreg 
 		generic map (
			size => 1,
			buswidth => BusWidth,
			invert => false
			)
		port map (
			clk  => clklow,
         ibus => ibus,
         obus => obus,
         load => LoadIDROMWEn,
         read => ReadIDROMWEn,
			clear => '0',
         dout => IDROMWen
		); 
		 		

	IDROM_2X_I30s: if (ConnsWithI30 = 2) and (IOPorts = 2)  generate
		IDROM : entity IDROM
			generic map (
				idromtype => IDROMType,
				offsettomodules => OffsetToModules,
				offsettopindesc => OffsetToPinDesc,
				boardnamelow => BoardNameLow,
				boardnamehigh => BoardNameHigh,
				fpgasize => FPGASize,
				fpgapins => FPGAPins,
				ioports => IOPorts,
				iowidth => IOWidth,
				portwidth => PortWidth,		
				clocklow => ClockLow,
				clockhigh => ClockHigh,
				inststride0 => InstStride0,
				inststride1 => InstStride1,
				regstride0 => RegStride0,
				regstride1 => RegStride1,
				pindesc => PinDesc_2xi30,
				moduleid => ModuleID_2xi30)
			port map (
				clk  => clklow, 
				we   => LoadIDROM,
				re   => ReadIDROM,
				radd => addr(9 downto 2),
				wadd => A(9 downto 2),
				din  => ibus, 
				dout => obus
		); 
	end generate;

	IDROM_3X_I30s: if I30Pinout and (ConnsWithI30 = 3) and (IOPorts = 3) generate
		IDROM : entity IDROM
			generic map (
				idromtype => IDROMType,
				offsettomodules => OffsetToModules,
				offsettopindesc => OffsetToPinDesc,
				boardnamelow => BoardNameLow,
				boardnamehigh => BoardNameHigh,
				fpgasize => FPGASize,
				fpgapins => FPGAPins,
				ioports => IOPorts,
				iowidth => IOWidth,
				portwidth => PortWidth,		
				clocklow => ClockLow,
				clockhigh => ClockHigh,
				inststride0 => InstStride0,
				inststride1 => InstStride1,
				regstride0 => RegStride0,
				regstride1 => RegStride1,
				pindesc => PinDesc_3xi30,
				moduleid => ModuleID_3xi30)
			port map (
				clk  => clklow, 
				we   => LoadIDROM,
				re   => ReadIDROM,
				radd => addr(9 downto 2),
				wadd => A(9 downto 2),
				din  => ibus, 
				dout => obus
		); 
	end generate;

	IDROM_4X_I30s: if I30Pinout and (ConnsWithI30 = 4) and (IOPorts = 4) generate
		IDROM : entity IDROM
			generic map (
				idromtype => IDROMType,
				offsettomodules => OffsetToModules,
				offsettopindesc => OffsetToPinDesc,
				boardnamelow => BoardNameLow,
				boardnamehigh => BoardNameHigh,
				fpgasize => FPGASize,