📄 hostmot2_import.tcl
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"A" "" "" "" "PROP_xilxBitgReadBk_Sec" "Enable Readback and Reconfiguration" "A" "" "" "" "PROP_xilxBitgStart_Clk" "CCLK" "A" "" "" "" "PROP_xilxBitgStart_Clk_Done" "6" "A" "" "" "" "PROP_xilxBitgStart_Clk_DriveDone" "false" "A" "" "" "" "PROP_xilxBitgStart_Clk_EnOut" "Default (5)" "A" "" "" "" "PROP_xilxBitgStart_Clk_MatchCycle" "Auto" "A" "" "" "" "PROP_xilxBitgStart_Clk_RelDLL" "Default (NoWait)" "A" "" "" "" "PROP_xilxBitgStart_Clk_RelSet" "Default (6)" "A" "" "" "" "PROP_xilxBitgStart_Clk_WrtEn" "4" "A" "" "" "" "PROP_xilxBitgStart_IntDone" "false" "A" "" "" "" "PROP_xilxMapAllowLogicOpt" "false" "A" "" "" "" "PROP_xilxMapCoverMode" "Speed" "A" "" "" "" "PROP_xilxMapDisableRegOrdering" "false" "A" "" "" "" "PROP_xilxMapGenInputK" "4" "A" "" "" "" "PROP_xilxMapPackRegInto" "For Inputs and Outputs" "A" "" "" "" "PROP_xilxMapReplicateLogic" "true" "A" "" "" "" "PROP_xilxMapReportDetail" "true" "A" "" "" "" "PROP_xilxMapSliceLogicInUnusedBRAMs" "false" "A" "" "" "" "PROP_xilxMapTimingDrivenPacking" "false" "A" "" "" "" "PROP_xilxMapTrimUnconnSig" "true" "A" "" "" "" "PROP_xilxNgdbldIOPads" "false" "A" "" "" "" "PROP_xilxNgdbldMacro" "" "A" "" "" "" "PROP_xilxNgdbldNTType" "Timestamp" "A" "" "" "" "PROP_xilxNgdbldPresHierarchy" "false" "A" "" "" "" "PROP_xilxNgdbldUR" "" "A" "" "" "" "PROP_xilxNgdbldUnexpBlks" "false" "A" "" "" "" "PROP_xilxNgdbld_AUL" "false" "A" "" "" "" "PROP_xilxPARplacerCostTable" "1" "A" "" "" "" "PROP_xilxPARplacerEffortLevel" "None" "A" "" "" "" "PROP_xilxPARrouterEffortLevel" "None" "A" "" "" "" "PROP_xilxPARstrat" "Normal Place and Route" "A" "" "" "" "PROP_xilxPARuseBondedIO" "false" "A" "" "" "" "PROP_xilxPostTrceAdvAna" "false" "A" "" "" "" "PROP_xilxPostTrceRpt" "Error Report" "A" "" "" "" "PROP_xilxPostTrceRptLimit" "3" "A" "" "" "" "PROP_xilxPostTrceStamp" "" "A" "" "" "" "PROP_xilxPostTrceTSIFile" "" "A" "" "" "" "PROP_xilxPostTrceUncovPath" "" "A" "" "" "" "PROP_xilxPreTrceAdvAna" "false" "A" "" "" "" "PROP_xilxPreTrceRpt" "Error Report" "A" "" "" "" "PROP_xilxPreTrceRptLimit" "3" "A" "" "" "" "PROP_xilxPreTrceUncovPath" "" "A" "" "" "" "PROP_xilxSynthAddBufg" "4" "A" "" "" "" "PROP_xilxSynthAddIObuf" "true" "A" "" "" "" "PROP_xilxSynthGlobOpt" "AllClockNets" "A" "" "" "" "PROP_xilxSynthKeepHierarchy" "No" "A" "" "" "" "PROP_xilxSynthKeepHierarchy_CPLD" "Yes" "A" "" "" "" "PROP_xilxSynthMacroPreserve" "true" "A" "" "" "" "PROP_xilxSynthMaxFanout" "100" "A" "" "" "" "PROP_xilxSynthRegBalancing" "No" "A" "" "" "" "PROP_xilxSynthRegDuplication" "true" "A" "" "" "" "PROP_xilxSynthXORPreserve" "true" "A" "" "" "" "PROP_xilxTriStateBuffTXMode" "On" "A" "" "" "" "PROP_xstAsynToSync" "false" "A" "" "" "" "PROP_xstAutoBRAMPacking" "false" "A" "" "" "" "PROP_xstBRAMUtilRatio" "100" "A" "" "" "" "PROP_xstBusDelimiter" "<>" "A" "" "" "" "PROP_xstCase" "Maintain" "A" "" "" "" "PROP_xstCoresSearchDir" "" "A" "" "" "" "PROP_xstCrossClockAnalysis" "false" "A" "" "" "" "PROP_xstEquivRegRemoval" "true" "A" "" "" "" "PROP_xstFsmStyle" "LUT" "A" "" "" "" "PROP_xstGenerateRTLNetlist" "Yes" "A" "" "" "" "PROP_xstGenericsParameters" "" "A" "" "" "" "PROP_xstHierarchySeparator" "/" "A" "" "" "" "PROP_xstIniFile" "" "A" "" "" "" "PROP_xstLibSearchOrder" "" "A" "" "" "" "PROP_xstOptimizeInsPrimtives" "false" "A" "" "" "" "PROP_xstPackIORegister" "Auto" "A" "" "" "" "PROP_xstReadCores" "true" "A" "" "" "" "PROP_xstSlicePacking" "true" "A" "" "" "" "PROP_xstSliceUtilRatio" "100" "A" "" "" "" "PROP_xstTristate2Logic" "Yes" "A" "" "" "" "PROP_xstUseClockEnable" "Yes" "A" "" "" "" "PROP_xstUseSyncReset" "Yes" "A" "" "" "" "PROP_xstUseSyncSet" "Yes" "A" "" "" "" "PROP_xstUseSynthConstFile" "true" "A" "" "" "" "PROP_xstUserCompileList" "" "A" "" "" "" "PROP_xstVeriIncludeDir_Global" "" "A" "" "" "" "PROP_xstVerilog2001" "true" "A" "" "" "" "PROP_xstVerilogMacros" "" "A" "" "" "" "PROP_xstWorkDir" "./xst" "A" "" "" "" "PROP_xstWriteTimingConstraints" "false" "A" "" "" "" "PROP_xst_otherCmdLineOptions" "" "A" "AutoGeneratedView" "VIEW_AbstractSimulation" "" "PROP_TopDesignUnit" "Architecture|i43hostmot2|Behavioral" "A" "AutoGeneratedView" "VIEW_AnalyzedDesign" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimIncreCompilation" "true" "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" "" "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimSpecifySearchDirectory" "" "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_ISimValueRangeCheck" "false" "A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_AnnotatedResultsFuse" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_AnnotatedResultsISim" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_BehavioralFuse" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_BehavioralSimulationISim" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_FPGAConfiguration" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_FPGAConfigureDevice" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_FPGAGeneratePROM" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_Map" "" "PROP_SmartGuide" "false" "A" "AutoGeneratedView" "VIEW_Map" "" "PROP_TopDesignUnit" "Module|i43hostmot2" "A" "AutoGeneratedView" "VIEW_Par" "" "PROP_TopDesignUnit" "Module|i43hostmot2" "A" "AutoGeneratedView" "VIEW_Post-MapAbstractSimulation" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_Post-MapPreSimulation" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_Post-ParAbstractSimulation" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_Post-ParFuse" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimCompileForHdlDebug" "true" "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimIncreCompilation" "true" "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" "" "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimSpecifySearchDirectory" "" "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_ISimValueRangeCheck" "false" "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_Post-ParSimulationISim" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_Post-SynthesisAbstractSimulation" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_Post-TranslateAbstractSimulation" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_Post-TranslatePreSimulation" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_PostAbstractSimulation" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimCompileForHdlDebug" "true" "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimIncreCompilation" "true" "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" "" "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimSpecifySearchDir" "" "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimSpecifySearchDirectory" "" "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_ISimValueRangeCheck" "false" "A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_Structural" "" "PROP_TopDesignUnit" "Module|i43hostmot2" "A" "AutoGeneratedView" "VIEW_TBWBehavioralFuse" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_TBWBehavioralSimulationISim" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_TBWPost-MapPreSimulation" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_TBWPost-ParFuse" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimCompileForHdlDebug" "true" "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimIncreCompilation" "true" "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" "" "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimSpecifySearchDirectory" "" "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_ISimValueRangeCheck" "false" "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_TBWPost-ParSimulationISim" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_TBWPost-TranslatePreSimulation" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimCompileForHdlDebug" "true" "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimIncreCompilation" "true" "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimSpecifyDefMacroAndValue" "" "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimSpecifySearchDirectory" "" "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_ISimValueRangeCheck" "false" "A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_Translation" "" "PROP_SmartGuide" "false" "A" "AutoGeneratedView" "VIEW_Translation" "" "PROP_TopDesignUnit" "Module|i43hostmot2" "A" "AutoGeneratedView" "VIEW_UpdatedBitstream" "" "PROP_TopDesignUnit" "" "A" "AutoGeneratedView" "VIEW_XSTAbstractSynthesis" "" "PROP_SmartGuide" "false" "A" "AutoGeneratedView" "VIEW_XSTAbstractSynthesis" "" "PROP_TopDesignUnit" "Architecture|i43hostmot2|Behavioral" "A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_TopDesignUnit" "Architecture|i43hostmot2|Behavioral" "A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_xstVeriIncludeDir" "" "A" "VIEW_Initial" "VIEW_Initial" "" "PROP_TopDesignUnit" "Architecture|i43hostmot2|Behavioral" "B" "" "" "" "PROP_AutoGenFile" "false" "B" "" "" "" "PROP_DevFamily" "Spartan3" "B" "" "" "" "PROP_FitterOptimization_xpla3" "Density" "B" "" "" "" "PROP_ISimCustomCompilationOrderFile" "" "B" "" "" "" "PROP_ISimCustomSimCmdFileName_behav_tb" "" "B" "" "" "" "PROP_ISimCustomSimCmdFileName_behav_tbw" "" "B" "" "" "" "PROP_ISimCustomSimCmdFileName_gen_tbw" "" "B" "" "" "" "PROP_ISimCustomSimCmdFileName_par_tb" "" "B" "" "" "" "PROP_ISimCustomSimCmdFileName_par_tbw" "" "B" "" "" "" "PROP_ISimGenVCDFile_par_tb" "false" "B" "" "" "" "PROP_ISimGenVCDFile_par_tbw" "false" "B" "" "" "" "PROP_ISimSimulationRun_behav_tb" "true" "B" "" "" "" "PROP_ISimSimulationRun_behav_tbw" "true" "B" "" "" "" "PROP_ISimSimulationRun_par_tb" "true" "B" "" "" "" "PROP_ISimSimulationRun_par_tbw" "true" "B" "" "" "" "PROP_ISimStoreAllSignalTransitions_behav_tb" "false" "B" "" "" "" "PROP_ISimStoreAllSignalTransitions_behav_tbw" "false" "B" "" "" "" "PROP_ISimStoreAllSignalTransitions_par_tb" "false" "B" "" "" "" "PROP_ISimStoreAllSignalTransitions_par_tbw" "false" "B" "" "" "" "PROP_MapEffortLevel" "Medium" "B" "" "" "" "PROP_MapLogicOptimization" "false" "B" "" "" "" "PROP_MapPlacerCostTable" "1" "B" "" "" "" "PROP_MapPowerReduction" "false" "B" "" "" "" "PROP_MapRegDuplication" "false" "B" "" "" "" "PROP_SimModelRenTopLevInstTo" "UUT" "B" "" "" "" "PROP_Simulator" "ISE Simulator (VHDL/Verilog)" "B" "" "" "" "PROP_SynthConstraintsFile" "" "B" "" "" "" "PROP_SynthMuxStyle" "Auto" "B" "" "" "" "PROP_SynthRAMStyle" "Auto" "B" "" "" "" "PROP_XPowerOptAdvancedVerboseRpt" "false" "B" "" "" "" "PROP_XPowerOptMaxNumberLines" "1000" "B" "" "" "" "PROP_XPowerOptUseTimeBased" "false" "B" "" "" "" "PROP_impactBaud" "None" "B" "" "" "" "PROP_impactConfigMode" "None" "B" "" "" "" "PROP_impactPort" "None" "B" "" "" "" "PROP_mpprViewPadRptForSelRslt" "" "B" "" "" "" "PROP_mpprViewParRptForSelRslt" "" "B" "" "" "" "PROP_parGenAsyDlyRpt" "false" "B" "" "" "" "PROP_parGenClkRegionRpt" "false" "B" "" "" "" "PROP_parGenSimModel" "false" "B" "" "" "" "PROP_parGenTimingRpt" "true" "B" "" "" "" "PROP_parMpprNodelistFile" "" "B" "" "" "" "PROP_parMpprParIterations" "3" "B" "" "" "" "PROP_parMpprResultsDirectory" "" "B" "" "" "" "PROP_parMpprResultsToSave" "" "B" "" "" "" "PROP_parPowerReduction" "false" "B" "" "" "" "PROP_xcpldFitDesInReg_xbr" "true" "B" "" "" "" "PROP_xcpldFitDesPtermLmt_xbr" "28" "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_DbgBitStr" "false" "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_LogicAllocFile" "false" "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_MaskFile" "false" "B" "" "" "" "PROP_xilxBitgReadBk_GenBitStr" "false" "B" "" "" "" "PROP_xilxMapPackfactor" "100" "B" "" "" "" "PROP_xilxPAReffortLevel" "Standard" "B" "" "" "" "PROP_xstMoveFirstFfStage" "true" "B" "" "" "" "PROP_xstMoveLastFfStage" "true" "B" "" "" "" "PROP_xstROMStyle" "Auto" "B" "" "" "" "PROP_xstSafeImplement" "No" "B" "AutoGeneratedView" "VIEW_Map" "" "PROP_ParSmartGuideFileName" "" "B" "AutoGeneratedView" "VIEW_Translation" "" "PROP_MapSmartGuideFileName" "" "C" "" "" "" "PROP_AceActiveName" "" "C" "" "" "" "PROP_CompxlibLang" "VHDL" "C" "" "" "" "PROP_CompxlibSimPath" "Search in Path" "C" "" "" "" "PROP_DevDevice" "xc3s400" "C" "" "" "" "PROP_DevFamilyPMName" "spartan3" "C" "" "" "" "PROP_ISimSimulationRunTime_behav_tb" "1000 ns" "C" "" "" "" "PROP_ISimSimulationRunTime_behav_tbw" "1000 ns" "C" "" "" "" "PROP_ISimSimulationRunTime_par_tb" "1000 ns" "C" "" "" "" "PROP_ISimSimulationRunTime_par_tbw" "1000 ns" "C" "" "" "" "PROP_ISimVCDFileName_par_tb" "xpower.vcd" "C" "" "" "" "PROP_ISimVCDFileName_par_tbw" "xpower.vcd" "C" "" "" "" "PROP_MapExtraEffort" "None" "C" "" "" "" "PROP_SimModelGenMultiHierFile" "false" "C" "" "" "" "PROP_XPowerOptBaseTimeUnit" "ps" "C" "" "" "" "PROP_XPowerOptNumberOfUnits" "1" "C" "" "" "" "PROP_impactConfigFileName" "" "C" "" "" "" "PROP_xilxPARextraEffortLevel" "None" "D" "" "" "" "PROP_CompxlibUni9000Lib" "true" "D" "" "" "" "PROP_CompxlibUniSimLib" "true" "D" "" "" "" "PROP_DevPackage" "tq144" "D" "" "" "" "PROP_Synthesis_Tool" "XST (VHDL/Verilog)" "E" "" "" "" "PROP_DevSpeed" "-4" "E" "" "" "" "PROP_PreferredLanguage" "VHDL" "F" "" "" "" "PROP_ChangeDevSpeed" "-4" "F" "" "" "" "PROP_SimModelTarget" "VHDL" "F" "" "" "" "PROP_hdlInstTempTargetLang" "VHDL" "F" "" "" "" "PROP_tbwTestbenchTargetLang" "VHDL" "F" "" "" "" "PROP_xilxPostTrceSpeed" "-4" "F" "" "" "" "PROP_xilxPreTrceSpeed" "-4" "G" "" "" "" "PROP_PostSynthSimModelName" "_synthesis.vhd" "G" "" "" "" "PROP_SimModelAutoInsertGlblModuleInNetlist" "true" "G" "" "" "" "PROP_SimModelGenArchOnly" "false" "G" "" "" "" "PROP_SimModelIncSdfAnnInVerilogFile" "true" "G" "" "" "" "PROP_SimModelIncSimprimInVerilogFile" "false" "G" "" "" "" "PROP_SimModelIncUnisimInVerilogFile" "false" "G" "" "" "" "PROP_SimModelIncUselibDirInVerilogFile" "false" "G" "" "" "" "PROP_SimModelNoEscapeSignal" "false" "G" "" "" "" "PROP_SimModelOutputExtIdent" "false" "G" "" "" "" "PROP_SimModelRenTopLevArchTo" "Structure" "G" "" "" "" "PROP_SimModelRenTopLevMod" "" "G" "AutoGeneratedView" "VIEW_Map" "" "PROP_PostMapSimModelName" "i43hostmot2_map.vhd" "G" "AutoGeneratedView" "VIEW_Par" "" "PROP_PostParSimModelName" "i43hostmot2_timesim.vhd" "G" "AutoGeneratedView" "VIEW_Post-MapAbstractSimulation" "" "PROP_tbwPostMapTestbenchName" "" "G" "AutoGeneratedView" "VIEW_Post-ParAbstractSimulation" "" "PROP_tbwPostParTestbenchName" "" "G" "AutoGeneratedView" "VIEW_Post-TranslateAbstractSimulation" "" "PROP_tbwPostXlateTestbenchName" "" "G" "AutoGeneratedView" "VIEW_Translation" "" "PROP_PostXlateSimModelName" "i43hostmot2_translate.vhd" "H" "" "" "" "PROP_SimModelBringOutGsrNetAsAPort" "false" "H" "" "" "" "PROP_SimModelBringOutGtsNetAsAPort" "false" "H" "" "" "" "PROP_SimModelPathUsedInSdfAnn" "Default" "H" "AutoGeneratedView" "VIEW_Map" "" "PROP_SimModelRenTopLevEntTo" "i43hostmot2" "H" "AutoGeneratedView" "VIEW_Par" "" "PROP_SimModelRenTopLevEntTo" "i43hostmot2" "H" "AutoGeneratedView" "VIEW_Structural" "" "PROP_SimModelRenTopLevEntTo" "i43hostmot2" "H" "AutoGeneratedView" "VIEW_Translation" "" "PROP_SimModelRenTopLevEntTo" "i43hostmot2" "I" "" "" "" "PROP_SimModelGsrPortName" "GSR_PORT" "I" "" "" "" "PROP_SimModelGtsPortName" "GTS_PORT" "I" "" "" "" "PROP_SimModelRocPulseWidth" "100" "I" "" "" "" "PROP_SimModelTocPulseWidth" "0"} HandleException { RestoreProcessProperties $iProjHelper $process_props } "A problem occured while restoring process properties." # library names and their members set libraries { } HandleException { RestoreSourceLibraries $iProjHelper $libraries } "A problem occured while restoring source libraries." # partition names for recreation set partition_names { } HandleException { RestorePartitions $partition_names } "A problem occured while restoring partitions." set opts_stream [ [Xilinx::Cit::FactoryCreate $::xilinx::Dpm::StreamBufferCompID ] GetInterface $xilinx::Prjrep::IStreamID ] $opts_stream WriteString "5" $opts_stream WriteString "5" $opts_stream WriteString "5" $opts_stream WriteString "5" $opts_stream WriteString "0" $opts_stream WriteString "0" $opts_stream WriteString "3" $opts_stream WriteString "1" $opts_stream WriteString "1" $opts_stream WriteString "1" $opts_stream WriteString "2" $opts_stream WriteString "0" $opts_stream WriteString "7" $opts_stream WriteString "./xst" $opts_stream WriteString "C:/ISE9/5i22/hostmot2/HostMot2_guide.ncd" $opts_stream WriteString "C:/ISE9/5i22/hostmot2/I20HostMot2_guide.ncd" $opts_stream WriteString "C:/ISE9/5i22/hostmot2/I22HostMot2_guide.ncd" $opts_stream WriteString "C:/ISE9/5i22/hostmot2/i43hostmot2_guide.ncd" $opts_stream WriteString "xpower.vcd" $opts_stream WriteString "xpower.vcd" $opts_stream WriteString "1" RestoreSourceControlOptions "$project_file" $opts_stream Release $opts_stream if { $srcctrl_comp != 0 } { set i_prjref [ $srcctrl_comp GetInterface $::xilinx::Dpm::IProjectHelperReferenceID ] $i_prjref Set iProjHelper } elseif {$iProjHelper != 0} { $iProjHelper Close } Release $iProjHelper # return back cd $old_working_dir}
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