regmap

来自「CNC 的开放码,EMC2 V2.2.8版」· 代码 · 共 952 行 · 第 1/3 页

0x2900  32 bit master DDS for all stepgens (compile time option,
may be disabled)

Step generator addition rate is (ClockLow*MasterDDSVal/2^32)

Probably just set to 0xffffffff for playing with

QuadratureCounter Type 2 (with timestamp)
32 bit register: bottom 16 bits are count, 
top 16 bits are timestamp of last change
Writes to counter register clear the counter.

0x3000 quad counter 0	
0x3004 quad counter 1	
0x3008 quad counter 2	
0x300C quad counter 3	
0x3010 quad counter 4	
0x3014 quad counter 5	
0x3018 quad counter 6	
0x301c quad counter 7	
...

The time stamp allows reciprocal time (DeltaCount/DeltaTime) 
velocity calculation for better estimation of motor velocity 
at low counts/sample interval


QuadratureCounter latch/Control register
32 bit register: top 16 bits are latched (by index) count, 
bottom 16 bits is control register

0x3100 quad counter latch/CCR 0	
0x3104 quad counter latch/CCR 1	
0x3108 quad counter latch/CCR 2	
0x310C quad counter latch/CCR 3	
0x3110 quad counter latch/CCR 4	
0x3114 quad counter latch/CCR 5	
0x3118 quad counter latch/CCR 6	
0x311c quad counter latch/CCR 7	
...

Bit 31..16 = Latched count (Latch on index)

Bit15	Quad Error: set if quadrature sequence error
Bit14	AB mask polarity: A*B must be high for index gate
Bit13	xx
Bit12	xx
Bit11   Quad filter (0=3 clocks 1=15 clocks)
Bit10	CounterMode 0 = Quadrature, 1 = up/down
Bit9	UseIndexMask 1= use mask
Bit8	IndexMask Polarity 1=active high
Bit7	ABgateIndex 1=gate index signal with A,B
Bit6	JustOnce 1= ClearOnIndex or LatchOnIndex happen only once
Bit5	ClearOnIndex 1=Clear count on index 
Bit4	LatchOnIndex 1=Latch count on index
Bit3	IndexPol 1 = active high
Bit2	read only realtime index signal
Bit1	read only realtime B signal
Bit0	read only realtime A signal

0x3200  TSSDiv 16 bit time stamp programmable divider (in LSBs) (R\W)

Sets quadrature counter reference clock for timestamp.

Timestamp count rate is ClockLow/(TSDiv+2). 
Any divisor with MSB set = divide by 1

0x3300  TSCount 16 bit time stamp counter (read only) 

0x3400  QfilterRate 12 bit Quadrature counter filter rate
count rate is ClockLow/(QFilterRate+2). 
Any divisor with MSB set = divide by 1


MuxedQuadratureCounter Type 2 (with timestamp)
Note: Multiplexed counters have same register bits but differing
count rate limits than normal quadrature counters

32 bit register: bottom 16 bits are count, 
top 16 bits are timestamp of last change
Writes to counter register clear the counter.

0x3500 quad counter 0	
0x3504 quad counter 1	
0x3508 quad counter 2	
0x350C quad counter 3	
0x3510 quad counter 4	
0x3514 quad counter 5	
0x3518 quad counter 6	
0x351c quad counter 7	
...

The time stamp allows reciprocal time (DeltaCount/DeltaTime) 
velocity calculation for better estimation of motor velocity 
at low counts/sample interval

MuxedQuadratureCounter latch/Control register
32 bit register: top 16 bits are latched (by index) count, 
bottom 16 bits is control register

0x3600 quad counter latch/CCR 0	
0x3604 quad counter latch/CCR 1	
0x3608 quad counter latch/CCR 2	
0x360C quad counter latch/CCR 3	
0x3610 quad counter latch/CCR 4	
0x3614 quad counter latch/CCR 5	
0x3618 quad counter latch/CCR 6	
0x361c quad counter latch/CCR 7	
...

Bit 31..16 = Latched count (Latch on index)

Bit15	Quad Error: set if quadrature sequence error
Bit14	AB mask polarity: A*B must be high for index gate
Bit13	xx
Bit12	xx
Bit11   Quad filter (0=3 clocks 1=15 clocks)
Bit10	CounterMode 0 = Quadrature, 1 = up/down
Bit9	UseIndexMask 1= use mask
Bit8	IndexMask Polarity 1=active high
Bit7	ABgateIndex 1=gate index signal with A,B
Bit6	JustOnce 1= ClearOnIndex or LatchOnIndex happen only once
Bit5	ClearOnIndex 1=Clear count on index 
Bit4	LatchOnIndex 1=Latch count on index
Bit3	IndexPol 1 = active high
Bit2	read only realtime index signal
Bit1	read only realtime B signal
Bit0	read only realtime A signal

0x3700  MuxedTSSDiv 16 bit time stamp programmable divider (in LSBs) (R\W)

Sets quadrature counter reference clock for timestamp.

MuxedTimestamp count rate is ClockLow/(MuxedTSDiv+2). 
Any divisor with MSB set = divide by 1

0x3800  MuxedTSCount 16 bit time stamp counter (read only) 

0x3900  QfilterRate 12 bit Quadrature counter filter rate
count rate is ClockLow/(QFilterRate+2). 
Any divisor with MSB set = divide by 1

Notes about quadrature filter rate:

QFilterRate sets the sampling rate for all quadrature counters input filters.
Input filtering should be set with as long a time constant as possible, 
especially when using TTL encoders.

The time constant chosen should give a fair (say 30%) margin of quadrature 
counter maximum count rate above the hardwares maximum possible count rate.

For example with a 33MHz ClockLow and QfilterRate = 0xFFF (divide by one):

With the filter bit off, the the input filter requires 3 clocks to 
recognize an input change = ~90 nS. This gives a maximum input frequency 
of 1/180 nS = ~5MHz or a maximum quadrature (4X) count rate of ~ 16MHz 
(limited to 1/2 of 33 MHz) 

With the filter bit on, the the input filter requires 15 clocks to 
recognize an input change = ~450 nS. This gives a maximum input frequency 
of 1/900 nS = ~1.1MHz or a maximum quadrature (4X) count rate of ~ 4.4 MHz

This is still much faster than needed for most applications so the QFilterRate
register allows lowering the filter sample rate. For example with the 
Qfilterrate register set to divide by 10 (QFilterRate loaded with 8), 
the input filter sample rate at 33 MHz ClockLow would be 3.3 MHz:

With the filter bit off, the the input filter requires 3 clocks to 
recognize an input change = ~900 nS. This gives a maximum input frequency 
of 1/1800 nS = ~500 KHz or a maximum quadrature (4X) count rate of ~ 2MHz

With the filter bit on, the the input filter requires 15 clocks to 
recognize an input change = ~4500 nS. This gives a maximum input frequency 
of 1/9000 nS = ~110 KHz or a maximum quadrature (4X) count rate of ~ 440 KHz

440 KHz is adequate for most normal applications = 13200 RPM with a 500 line 
(2000 count) encoder, and has the benefit that noise rejection is very good, 
input noise pulses less than 4500 nS will be ignored. Most PWM generated 
noise pulses tend to be short, determined by the PWM voltage and the time 
constant of the PWM to encoder wire capacitance and the encoder output 
resistance. This output resistance is often quite high in low cost TTL 
encoders, with outputs that are just open collector comparators with pullup 
resistors. These encoders are very susceptible to low going noise pulses, and 
benefit greatly by maximizing the filter time constant.

Lowering the quadrature filter rate has the disadvantage of reducing the 
quadrature edge timing resolution when inverse time velocity estimation is 
used, however, this is normally not a problem as even at a 1 MHz sample rate, 
the 1 uSec timing uncertainty will be swamped out by the quadrature phase 
inaccuracies in typical encoders. 

For multiplexed quadrature counters, the multiplex channel rate is 1/2 the 
filter rate. Due to flat cable signal integrity and time of flight issues the 
multiplex channel rate should not be higher than 8 MHz, with lower rates 
needed with longer cable runs. This means that the filter rate should not 
be set higher than 16 MHz. The hardware default for the multiplexed flter 
rate register is set to divide by 4 which gives a multiplex rate of
4.166 MHz with a 33 MHx clklow and 6.25 MHz with a 50 MHZ clklow. 

The hardware default filter rate is set to divide by 1 for non-multiplexed 
counters.


PWM generators (With FPGA compile time constant PWM width = 13)

0x4000	PWMVal 0 Right justified 9..12 bit PWM in bits 27..16 DIR is bit 31
0x4004	PWMVal 1 Right justified 9..12 bit PWM in bits 27..16 DIR is bit 31
0x4008	PWMVal 2 Right justified 9..12 bit PWM in bits 27..16 DIR is bit 31
0x400C	PWMVal 3 Right justified 9..12 bit PWM in bits 27..16 DIR is bit 31
0x4010	PWMVal 4 Right justified 9..12 bit PWM in bits 27..16 DIR is bit 31
0x4014	PWMVal 5 Right justified 9..12 bit PWM in bits 27..16 DIR is bit 31
0x4018	PWMVal 6 Right justified 9..12 bit PWM in bits 27..16 DIR is bit 31
0x401C	PWMVal 7 Right justified 9..12 bit PWM in bits 27..16 DIR is bit 31
...
 	
PWM mode registers 6 bits

Bit 1,0 = width select  (With FPGA compile time constant PWM width = 13)
00 = 9 bit PWM
01 = 10 bit PWM
10 = 11 bit PWM
11 = 12 bit PWM

Bit 2 = PWM mode select
0 = Straight (Sawtooth) PWM     
1 = Symmetrical (Triangle) PWM

Bit 4,3 = PWM output mode select
00 = Normal Sign Magnitude PWM&DIR outputs normal
01 = Normal Sign Magnitude PWM&DIR outputs swapped (for locked antiphase)
10 = Up/down mode
11 = PDM mode (12 bits)

Bit 5 = Double Buffered mode
When bit 5 is set, the PWMval register is not updated until the beginning of a 
PWM cycle, avoiding extra transitions in the output PWM waveform. This adds 
an extra delay of 0 to PWMWidth/PWMClock (normal mode) or PWMWidth*2/PWMClock
(Symmetrical mode) between when the host writes the PWMVal register and the 
PWM output is updated. 


0x4100 PWM mode select register 0
0x4104 PWM mode select register 1
0x4108 PWM mode select register 2
0x410C PWM mode select register 3
0x4110 PWM mode select register 4
0x4114 PWM mode select register 5
0x4118 PWM mode select register 6
0x411C PWM mode select register 7
...

0x4200  16 bit PWM gen master rate DDS (PWMCLOCK = CLKHIGH*Rate/65536) 
        PWM rate will be PWMCLOCK/(2^PWMBITS) for normal PWM
        and PWMCLOCK/(2^(PWMBITS+1)) for symmetrical mode PWM.

0x4300	16 bit PDM gen master rate DDS (PDMCLOCK = CLKHIGH*Rate/65536) 
        PDM rate will be PDMCLOCK/(4096).

0x4400	Enable register for PWM. Doesn't actually change PWM but is used for 
        enabling PWM driven devices (the ENA pin). 1 bit per PWM channel. 
        Active high --> '1' means enabled = '0' output pin level.

Bit 0   PWM channel 0 enable
Bit 1   PWM channel 1 enable
Bit 2   PWM channel 2 enable

PWM/PDM Notes: 

1. For 7I33, 7I33T and 7I47 that filter the PWM to generate analog voltages, 
   PDM mode should be used. Optimum PDM rate for best trade-off between ripple 
   and linearity for 7I33 and 7I33T is about 6 MHz (PDM rate register approx
   0x0fff) This gives about 12 bits of resolution and 10 bit linearity/ripple.

2. Double buffering should be used where the PWM directly drives an HBridge. 
   Double buffering prevents extra transitions on the PWM output doe to host 
   updates  which waste power in switching losses. Double buffering should 
   _not_ be used with PDM output! Double Buffering will add a 0 to 1/PWMRate 
   delay in the PWM output if the host does not update the PWM generator
   synchronously with the PWM rate..


UART TX data register
Different offsets push different numbers of bytes on xmit FIFO
Didn't use byte enables for compatibility with other (non PCI) 32 bit interfaces

0x4500 UART TXdata 0 (push 1 byte)
0x4504 UART TXData 0 (push 2 bytes)
0x4508 UART TXData 0 (push 3 bytes)
0x450C UART TXData 0 (push 4 bytes)
0x4510 UART TXdata 1 (push 1 byte)
0x4514 UART TXData 1 (push 2 bytes)
0x4518 UART TXData 1 (push 3 bytes)
0x451C UART TXData 1 (push 4 bytes)
0x4520 UART TXdata 2 (push 1 byte)
0x4524 UART TXData 2 (push 2 bytes)
0x4528 UART TXData 2 (push 3 bytes)
0x452C UART TXData 2 (push 4 bytes)
0x4530 UART TXdata 3 (push 1 byte)
0x4534 UART TXData 3 (push 2 bytes)
0x4538 UART TXData 3 (push 3 bytes)
0x453C UART TXData 3 (push 4 bytes)
...

UART TX FIFO count register = number slots used in FIFO, 
pushes less than one 32 bit word use a hole word slot, in other words, 
TX FIFO is 16 32 bit words deep, but 16 one byte pushes will fill, 
so TX FIFO capacity is 16 Bytes for byte pushes, but 64 bytes with 
16 doubleword pushes.
Writes to the FIFO count register clear the FIFO.

0x4600 UART TXFIFO Count 0
0x4604 UART TXFIFO Count 1
0x4608 UART TXFIFO Count 2
0x460C UART TXFIFO Count 3
...

TX Bitrate select register. TX bitrate is generated by a 16 bit 
phase accumulator. Bitrate is: TXBitrate/65536*ClockLow