regmap

来自「CNC 的开放码,EMC2 V2.2.8版」· 代码 · 共 952 行 · 第 1/3 页

HostMot2 Register map in offsets from 32 bit memory base address

Note the following addresses are standard but driver should use IDROM info
instead of this table.

Also, number of special functions (counters, PWMGens etc) is determined 
by configuration.
Additional registers are always at increasing doubleword boundaries 
with the exception of UART data FIFOs. 
(this difference with UARTS make be fixed by using byte enables later)

First ID stuff

0x0100	Config cookie 	= 0x55AACAFE
0x0104	First 4 characters of configuration name
0x0108	Last 4 characters of configuration name
0x010C	Offset to IDROM location (normally 0x00000400)

0x0400	Normal IDROM location

0x400	IDROMType		2 for this type
0x404	OffsetToModules		64 for this type
0x408	OffsetToPindesc		512 for this type
0x40C	BoardNameLow		
0x410	BoardNameHigh
0x414	FPGA size
0x418	FPGA pins
0x41C	IOPorts			
0x420	IOWidth
0x424	PortWidth		Normally 24
0x428	ClockLow		In Hz	(note:on 5I20/4I65 = PCI clock 
                                guessed as 33.33 MHz)
0x42C	ClockHigh		In Hz
0x430	InstanceStride0
0x434	InstanceStride1
0x438	RegisterStride0
0x43C	RegisterStride1

0x440..	Module descriptions 0 through 31
Each module descriptor is three doublewords with the following record structure:

0x440: (from least to most significant order)
GTag(0		(byte) = General function tag
Version(0)	(byte) = module version
ClockTag(0)	(byte) = Whether module uses ClockHigh or ClockLow
Instances(0)	(byte) = Number of instances of module in configuration
BaseAddress(0)	(word) = offset to module. This is also specific register = Tag
Registers(0)	(byte) = Number of registers per module
MPBitmap(0)	(Double) = bit map of which registers are multiple 
                '1' = multiple, LSb = reg(0)

0x44C: (from least to most significant order)
GTag(1)		(byte) = General function tag
Version(1)	(byte) = module version
ClockTag(1)	(byte) = Whether module uses ClockHigh or ClockLow
Instances(1)	(byte) = Number of instances of module in configuration
BaseAddress(1)	(word) = offset to module. This is also specific register = Tag
Registers(1)	(byte) = Number of registers per module
MPBitmap(1)	(Double) = bit map of which registers are multiple 
                '1' = multiple, LSb = reg(0)


0 GTag marks end of module descriptors


0x600 Pin descriptors 0 through 127. 
There is one Pin Descriptor for each I/O pin.
Each pin descriptor is a doubleword with the following record structure:

0x600: (from least to most significant order)
SecPin(0)	(byte) = Which pin of secondary function connects here 
                eg: A,B,IDX. 
                         Output pins have bit 7 = '1'
SecTag(0)	(byte) = Secondary function type (PWM,QCTR etc). 
                Same as module GTag
SecUnit(0)	(byte) = Which secondary unit or channel connects here
PrimaryTag(0)	(byte) = Primary function tag (normally I/O port)

0x604:(from least to most significant order)
SecPin(1)	(byte) = Which pin of secondary function connects here 
                eg: A,B,IDX. 
                         Output pins have bit 7 = '1'
SecTag(1)	(byte) = Secondary function type (PWM,QCTR etc). 
                Same as module GTag
SecUnit(1)	(byte) = Which secondary unit or channel connects here
PrimaryTag(1)	(byte) = Primary function tag (normally I/O port)

...

0 primary function tag marks end of pins

0x0800  1 bit IDROM write enable bit: high=Enable writes

0x0900	IRQDiv 

16 bit divider of selected PWMreference output bit. Divides by n+2.

0x0A00	IRQStatus

Bit 2..4  Select which PWM reference counter bit is used as IRQ divider source:
000 = PWMRefcount(MSB-7)
001 = PWMRefcount(MSB-6)
010 = PWMRefcount(MSB-5)
011 = PWMRefcount(MSB-4)
100 = PWMRefcount(MSB-3)
101 = PWMRefcount(MSB-2)
110 = PWMRefcount(MSB-1)
111 = PWMRefcount(MSB)

Bit 1 = Irq mask: 0 = masked

Bit 0 = IRQ status (R/W)

0x0B00	ClearIRQ: Writes here clear IRQ 


0x0C00	WatchdogTimer (R/W

32 bit watchdog timer.If MSB is set, watchdog is disabled.
Timeout is WatchdogTimer+1/CLKLOW. Currently all watchdog does 
is clear GPIO DDR, and OpenDrain registers setting all GPIO to 
inputs (high with pullups)

0x0D00	WatchDogStatus

Bit 0 = Watchdog has bitten status (1 = you been bit)

0x0E00

Watchdog Cookie location

0x5A written to 8 MSbs will reset watchdog to previously written 
timeout value.


0x1000	I/O port  0..23
0x1004  I/O port 24..47
0x1008  I/O port 48..71
0x100C  I/O port 72..95
0x1010  I/O port 96..127

Writes write to output register, reads read pin status

0x1100	DDR for I/O port  0..23
0x1104  DDR for I/O port  24..47
0x1108  DDR for I/O port  48..71
0x110C  DDR for I/O port  72..95

'1' bit in DDR register makes corresponding GPIO bit an output

0x1200  AltSourceReg for I/O port  0..23
0x1204  AltSourceReg for I/O port  24..47
0x1208  AltSourceReg for I/O port  48..71
0x120C  AltSourceReg for I/O port  72..95

'1' bit in AltSource register makes corresponding GPIO bit data source 
come from Alternate source for that bit instead of output register.

0x1300	OpenDrainSelect for I/O port  0..23
0x1304  OpenDrainSelect for I/O port  24..47
0x1308  OpenDrainSelect for I/O port  48..71
0x130C  OpenDrainSelect for I/O port  72..95

'1' bit in OpenDrainSelect register makes corresponding GPIO an 
open drain output.
If OpenDrain is selected for an I/O bit , the DDR register is ignored.

0x1400	OutputInvert for I/O port  0..23
0x1404  OutputInvert for I/O port  24..47
0x1408  OutputInvert for I/O port  48..71
0x140C  OutputInvert for I/O port  72..95

A '1' bit in the OutputInv register inverts the cooresponding output bit.
This may be the output register bit or alternate source. The input is not 
inverted.


**************************************************
Step/dir generators currently 48 bit accum = 16 bits full step, 
32 fractional step/rate

 Step rate registers : Write only

0x2000	32 bit rate register for StepGen 0 
0x2004 	32 bit rate register for StepGen 1  
0x2008	32 bit rate register for StepGen 2
0x200C	32 bit rate register for StepGen 3
0x2010	32 bit rate register for StepGen 4
0x2014	32 bit rate register for StepGen 5
0x2018	32 bit rate register for StepGen 6
0x201C	32 bit rate register for StepGen 7
...

 32 bit top of accumulator = 16.16 fullstep.fractionalstep : Read/write

0x2100	32 bit full.fractional accum for StepGen 0
0x2104 	32 bit full.fractional accum for StepGen 1  
0x2108	32 bit full.fractional accum for StepGen 2
0x210C	32 bit full.fractional accum for StepGen 3
0x2110	32 bit full.fractional accum for StepGen 4
0x2114	32 bit full.fractional accum for StepGen 5
0x2118	32 bit full.fractional accum for StepGen 6
0x211C	32 bit full.fractional accum for StepGen 7
...

Mode registers (2 bits Write only)
00 = Step/Dir
01 = Up/Down
10 = Quadrature
11 = Table Driven

0x2200	2 bit mode register for StepGen 0
0x2204 	2 bit mode register for StepGen 1  
0x2208	2 bit mode register for StepGen 2
0x220C	2 bit mode register for StepGen 3
0x2210	2 bit mode register for StepGen 4
0x2214	2 bit mode register for StepGen 5
0x2218	2 bit mode register for StepGen 6
0x221C	2 bit mode register for StepGen 7
...

DIR Setup time = how long DIR must be valid before step 
pulses may be issued
Max time for 14 bits at ClockLow = 33 MHz = ~480 uS. 
At ClockLow = 50 MHz = ~320 uS (dont use 0)

Write only

0x2300	14 bit DIR setup time register for StepGen 0
0x2304 	14 bit DIR setup time register for StepGen 1  
0x2308	14 bit DIR setup time register for StepGen 2
0x230C	14 bit DIR setup time register for StepGen 3
0x2310	14 bit DIR setup time register for StepGen 4
0x2314	14 bit DIR setup time register for StepGen 5
0x2318	14 bit DIR setup time register for StepGen 6
0x231C	14 bit DIR setup time register for StepGen 7
...

DIR Hold time = how long DIR most remain valid after 
a step pulse has been issued 
Max time for 14 bits at ClockLow = 33 MHz = ~480 mS. 
At ClockLow = 50 MHz = ~320 mS (dont use 0)

Write only

0x2400	14 bit DIR hold time register for StepGen 0
0x2404 	14 bit DIR hold time register for StepGen 1  
0x2408	14 bit DIR hold time register for StepGen 2
0x240C	14 bit DIR hold time register for StepGen 3
0x2410	14 bit DIR hold time register for StepGen 4
0x2414	14 bit DIR hold time register for StepGen 5
0x2418	14 bit DIR hold time register for StepGen 6
0x241C	14 bit DIR hold time register for StepGen 7
...

Pulse length = Active time of output pulse.
Max time for 14 bits at ClockLow = 33 MHz = ~480 uS. 
At ClockLow = 50 MHz = ~320 uS (dont use 0)

Write only

0x2500	14 bit pulse width register for StepGen 0
0x2504 	14 bit pulse width register for StepGen 1  
0x2508	14 bit pulse width register for StepGen 2
0x250C	14 bit pulse width register for StepGen 3
0x2510	14 bit pulse width register for StepGen 4
0x2514	14 bit pulse width register for StepGen 5
0x2518	14 bit pulse width register for StepGen 6
0x251C	14 bit pulse width register for StepGen 7
...

Pulse Idle = Inactive time of output pulse.
Max time for 14 bits at ClockLow = 33 MHz = ~480 uS. 
At ClockLow = 50 MHz = ~320 uS (dont use 0)

Write only

0x2600	14 bit pulse idle width register for StepGen 0
0x2604 	14 bit pulse idle width register for StepGen 1  
0x2608	14 bit pulse idle width register for StepGen 2
0x260C	14 bit pulse idle width register for StepGen 3
0x2610	14 bit pulse idle width register for StepGen 4
0x2614	14 bit pulse idle width register for StepGen 5
0x2618	14 bit pulse idle width register for StepGen 6
0x261C	14 bit pulse idle width register for StepGen 7
...

Output sequence table. This is a single write location where the 
table sequence data for table driven step generator output is stored.
Data is written sequentially here from last to first data word in the 
sequence. Default table width is 6 bits.
Table data is in LSBs of written word.

0x2700	Table sequence data setup register for StepGen 0
0x2704	Table sequence data setup register for StepGen 1
0x2708	Table sequence data setup register for StepGen 2
0x270C	Table sequence data setup register for StepGen 3
0x2710	Table sequence data setup register for StepGen 4
0x2714	Table sequence data setup register for StepGen 5
0x2718	Table sequence data setup register for StepGen 6
0x271c	Table sequence data setup register for StepGen 7
...

TableLength register: 4 bit register that determines table sequence 
length. Sequence length is TableLength+1, Maximum length is 16 steps


0x2800	Table sequence length register for StepGen 0
0x2804	Table sequence length register for StepGen 1
0x2808	Table sequence length register for StepGen 2
0x280C	Table sequence length register for StepGen 3
0x2810	Table sequence length register for StepGen 4
0x2814	Table sequence length register for StepGen 5
0x2818	Table sequence length register for StepGen 6
x281c	Table sequence length register for StepGen 7

...