cc1100.c

s3c2410开发板中使用cc1100无线模块的linux驱动

#include "CC1100.h"


#define 	WRITE_BURST     	0x40						//l�д�
#define 	READ_SINGLE     	0x80						//�
#define 	READ_BURST      	0xC0						//l��
#define 	BYTES_IN_RXFIFO     0x7F  						//�ջ�����
#define 	CRC_OK              0x80 						//CRCУ�ͨλ�


 const RF_SETTINGS rfSettings = {
	0x00,
    0x08,   // FSCTRL1   Frequency synthesizer control.
    0x00,   // FSCTRL0   Frequency synthesizer control.
    0x10,   // FREQ2     Frequency control word, high byte.
    0xA7,   // FREQ1     Frequency control word, middle byte.
    0x62,   // FREQ0     Frequency control word, low byte.
    0x5B,   // MDMCFG4   Modem configuration.
    0xF8,   // MDMCFG3   Modem configuration.
    0x03,   // MDMCFG2   Modem configuration.
    0x22,   // MDMCFG1   Modem configuration.
    0xF8,   // MDMCFG0   Modem configuration.

    0x00,   // CHANNR    Channel number.
    0x47,   // DEVIATN   Modem deviation setting (when FSK modulation is enabled).
    0xB6,   // FREND1    Front end RX configuration.
    0x10,   // FREND0    Front end RX configuration.
    0x18,   // MCSM0     Main Radio Control State Machine configuration.
    0x1D,   // FOCCFG    Frequency Offset Compensation Configuration.
    0x1C,   // BSCFG     Bit synchronization Configuration.
    0xC7,   // AGCCTRL2  AGC control.
    0x00,   // AGCCTRL1  AGC control.
    0xB2,   // AGCCTRL0  AGC control.

    0xEA,   // FSCAL3    Frequency synthesizer calibration.
    0x2A,   // FSCAL2    Frequency synthesizer calibration.
    0x00,   // FSCAL1    Frequency synthesizer calibration.
    0x11,   // FSCAL0    Frequency synthesizer calibration.
    0x59,   // FSTEST    Frequency synthesizer calibration.
    0x81,   // TEST2     Various test settings.
    0x35,   // TEST1     Various test settings.
    0x09,   // TEST0     Various test settings.
    0x0B,   // IOCFG2    GDO2 output pin configuration.
    0x06,   // IOCFG0D   GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.

    0x04,   // PKTCTRL1  Packet automation control.
    0x05,   // PKTCTRL0  Packet automation control.
    0x00,   // ADDR      Device address.
    0x0c    // PKTLEN    Packet length.
};

// PATABLE (0 dBm output power)
INT8U PaTabel[8] = {0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60};

static void delay(unsigned int s)
{
	__udelay(s);
}


void halWait(INT16U timeout) 
{
	__udelay(timeout);
}

void SpiInit(void)
{
//	CSN=0;
	s3c2410_gpio_setpin(CSN,0);
//	SCK=0;
	s3c2410_gpio_setpin(SCK,0);
//	CSN=1;
	s3c2410_gpio_setpin(CSN,1);
}

void CpuInit(void)
{
	SpiInit();
	delay(500);
}


INT8U SpiTxRxByte(INT8U dat)
{
	INT8U i,temp;
	temp = 0;
//	SCK = 0;
	s3c2410_gpio_setpin(SCK,0);
	for(i=0; i<8; i++)
	{
		if(dat & 0x80)
		{
//			MOSI = 1;
			s3c2410_gpio_setpin(MOSI,1);
		}
		else 
//			MOSI = 0;
			s3c2410_gpio_setpin(MOSI,0);
		dat <<= 1;
//		SCK = 1; 
		s3c2410_gpio_setpin(SCK,1);
		__udelay(1);
		temp <<= 1;
		if(s3c2410_gpio_getpin(MISO))
			temp++; 
//		SCK = 0;
		s3c2410_gpio_setpin(SCK,0);
//		_nop_();
		__udelay(1);	
	}
	return temp;
}

void RESET_CC1100(void) 
{
//	CSN = 0; 
	s3c2410_gpio_setpin(CSN,0);
	while (s3c2410_gpio_getpin(MISO));
    	SpiTxRxByte(CCxxx0_SRES); 		//д�λ��
	while (s3c2410_gpio_getpin(MISO)); 
//    CSN = 1; 
	s3c2410_gpio_setpin(CSN,1);
}

void POWER_UP_RESET_CC1100(void) 
{
//	CSN = 1; 
	s3c2410_gpio_setpin(CSN,1);
	halWait(1); 
//	CSN = 0; 
	s3c2410_gpio_setpin(CSN,0);
	halWait(1); 
//	CSN = 1; 
	s3c2410_gpio_setpin(CSN,1);
	halWait(41); 
	RESET_CC1100();   		//λCC1100
}

void halSpiWriteReg(INT8U addr, INT8U value) 
{
//    	CSN = 0;
	s3c2410_gpio_setpin(CSN,0);
    	while (s3c2410_gpio_getpin(MISO));           //������ISOΪͲ���Ϊ�ʱ����
    	SpiTxRxByte(addr);		//д�
    	SpiTxRxByte(value);		//��
//    	CSN = 1;
	s3c2410_gpio_setpin(CSN,1);
}

void halSpiWriteBurstReg(INT8U addr, INT8U *buffer, INT8U count) 
{
    	INT8U i, temp;
	temp = addr | WRITE_BURST;
//    	CSN = 0;
	s3c2410_gpio_setpin(CSN,0);
    	while (s3c2410_gpio_getpin(MISO));
    	SpiTxRxByte(temp);
    	for (i = 0; i < count; i++)
 	{
        	SpiTxRxByte(buffer[i]);
    	}
//    	CSN = 1;
	s3c2410_gpio_setpin(CSN,1);
}

void halSpiStrobe(INT8U strobe) 
{
//    	CSN = 0;
	s3c2410_gpio_setpin(CSN,0);    
	while (s3c2410_gpio_getpin(MISO));
    	SpiTxRxByte(strobe);		//��
//    	CSN = 1;
	s3c2410_gpio_setpin(CSN,1);
}

INT8U halSpiReadReg(INT8U addr) 
{
	INT8U temp, value;
    	temp = addr|READ_SINGLE;//|Ĵ���
//	CSN = 0;
	s3c2410_gpio_setpin(CSN,0);	
	while (s3c2410_gpio_getpin(MISO));
	SpiTxRxByte(temp);
	value = SpiTxRxByte(0);
//	CSN = 1;
	s3c2410_gpio_setpin(CSN,1);
	return value;
}

void halSpiReadBurstReg(INT8U addr, INT8U *buffer, INT8U count) 
{
    	INT8U i,temp;
	temp = addr | READ_BURST;		//д�Ҫu��üĴ��ַͶ��
//    	CSN = 0;
	s3c2410_gpio_setpin(CSN,0);
    	while (s3c2410_gpio_getpin(MISO));
	SpiTxRxByte(temp);   
    	for (i = 0; i < count; i++) 
	{
        	buffer[i] = SpiTxRxByte(0);
    	}
//    	CSN = 1;
	s3c2410_gpio_setpin(CSN,1);
}

INT8U halSpiReadStatus(INT8U addr) 
{
    	INT8U value,temp;
	temp = addr | READ_BURST;		//д�Ҫu�̬Ĵ���ͬʱд���
//    	CSN = 0;
	s3c2410_gpio_setpin(CSN,0);
    	while (s3c2410_gpio_getpin(MISO));
    	SpiTxRxByte(temp);
	value = SpiTxRxByte(0);
//	CSN = 1;
	s3c2410_gpio_setpin(CSN,1);	
	return value;
}

void halRfWriteRfSettings(void) 
{

	halSpiWriteReg(CCxxx0_FSCTRL0,  rfSettings.FSCTRL2);//��ӵ�
    // Write register settings
    halSpiWriteReg(CCxxx0_FSCTRL1,  rfSettings.FSCTRL1);
    halSpiWriteReg(CCxxx0_FSCTRL0,  rfSettings.FSCTRL0);
    halSpiWriteReg(CCxxx0_FREQ2,    rfSettings.FREQ2);
    halSpiWriteReg(CCxxx0_FREQ1,    rfSettings.FREQ1);
    halSpiWriteReg(CCxxx0_FREQ0,    rfSettings.FREQ0);
    halSpiWriteReg(CCxxx0_MDMCFG4,  rfSettings.MDMCFG4);
    halSpiWriteReg(CCxxx0_MDMCFG3,  rfSettings.MDMCFG3);
    halSpiWriteReg(CCxxx0_MDMCFG2,  rfSettings.MDMCFG2);
    halSpiWriteReg(CCxxx0_MDMCFG1,  rfSettings.MDMCFG1);
    halSpiWriteReg(CCxxx0_MDMCFG0,  rfSettings.MDMCFG0);
    halSpiWriteReg(CCxxx0_CHANNR,   rfSettings.CHANNR);
    halSpiWriteReg(CCxxx0_DEVIATN,  rfSettings.DEVIATN);
    halSpiWriteReg(CCxxx0_FREND1,   rfSettings.FREND1);
    halSpiWriteReg(CCxxx0_FREND0,   rfSettings.FREND0);
    halSpiWriteReg(CCxxx0_MCSM0 ,   rfSettings.MCSM0 );
    halSpiWriteReg(CCxxx0_FOCCFG,   rfSettings.FOCCFG);
    halSpiWriteReg(CCxxx0_BSCFG,    rfSettings.BSCFG);
    halSpiWriteReg(CCxxx0_AGCCTRL2, rfSettings.AGCCTRL2);
	halSpiWriteReg(CCxxx0_AGCCTRL1, rfSettings.AGCCTRL1);
    halSpiWriteReg(CCxxx0_AGCCTRL0, rfSettings.AGCCTRL0);
    halSpiWriteReg(CCxxx0_FSCAL3,   rfSettings.FSCAL3);
	halSpiWriteReg(CCxxx0_FSCAL2,   rfSettings.FSCAL2);
	halSpiWriteReg(CCxxx0_FSCAL1,   rfSettings.FSCAL1);
    halSpiWriteReg(CCxxx0_FSCAL0,   rfSettings.FSCAL0);
    halSpiWriteReg(CCxxx0_FSTEST,   rfSettings.FSTEST);
    halSpiWriteReg(CCxxx0_TEST2,    rfSettings.TEST2);
    halSpiWriteReg(CCxxx0_TEST1,    rfSettings.TEST1);
    halSpiWriteReg(CCxxx0_TEST0,    rfSettings.TEST0);
    halSpiWriteReg(CCxxx0_IOCFG2,   rfSettings.IOCFG2);
    halSpiWriteReg(CCxxx0_IOCFG0,   rfSettings.IOCFG0);    
    halSpiWriteReg(CCxxx0_PKTCTRL1, rfSettings.PKTCTRL1);
    halSpiWriteReg(CCxxx0_PKTCTRL0, rfSettings.PKTCTRL0);
    halSpiWriteReg(CCxxx0_ADDR,     rfSettings.ADDR);
    halSpiWriteReg(CCxxx0_PKTLEN,   rfSettings.PKTLEN);
}

void halRfSendPacket(INT8U *txBuffer, INT8U size) 
{
	halSpiWriteReg(CCxxx0_TXFIFO, size);
    	halSpiWriteBurstReg(CCxxx0_TXFIFO, txBuffer, size);	//д�Ҫ���
    	halSpiStrobe(CCxxx0_STX);		//��ģʽ���
    // Wait for GDO0 to be set -> sync transmitted
    	while (!s3c2410_gpio_getpin(GDO0));
    // Wait for GDO0 to be cleared -> end of packet
    	while (s3c2410_gpio_getpin(GDO0));
	halSpiStrobe(CCxxx0_SFTX);
}


void setRxMode(void)
{
    halSpiStrobe(CCxxx0_SRX);		//���̬
}

 INT8U halRfReceivePacket(INT8U *rxBuffer, INT8U *length) 
{
    	INT8U status[2];
    	INT8U packetLength;
    	if ((halSpiReadStatus(CCxxx0_RXBYTES) & BYTES_IN_RXFIFO)) //�ӵ�ֽ�Ϊ0
    	{
    		packetLength = halSpiReadReg(CCxxx0_RXFIFO);//s�һ�ֽڣ�ֽ���ݳ�
    		if (packetLength <= *length) 		//��Ҫ���ݳ���ڽ�յ�ݰij�
    		{
    			halSpiReadBurstReg(CCxxx0_RXFIFO, rxBuffer, packetLength); //s���յ��
    			*length = packetLength;				//ѽ��ݳȵ�޸�ǰ�ݵij�
        
    			// Read the 2 appended status bytes (status[0] = RSSI, status[1] = LQI)
    			halSpiReadBurstReg(CCxxx0_RXFIFO, status, 2); 	//s�RCУ�λ
    			halSpiStrobe(CCxxx0_SFRX);		//�ϴ�ջ�
    			return (status[1] & CRC_OK);			//�У�ɹؽ�ճɹ
    		}
    		else 
    		{
    			*length = packetLength;
    			halSpiStrobe(CCxxx0_SFRX);		//�ϴ�ջ�
    			return 0;
    		}
    	} 
    	else
    		return 0;
}