cc1100-backup.c

s3c2410开发板中使用cc1100无线模块的linux驱动

    0x88,   // TEST2     Various test settings.
    0x31,   // TEST1     Various test settings.
    0x0B,   // TEST0     Various test settings.
    0x0B,   // IOCFG2    GDO2 output pin configuration.
    0x06,   // IOCFG0D   GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.

    0x04,   // PKTCTRL1  Packet automation control.
	//0x05,   // PKTCTRL1  Packet automation control.	//�� 
    0x45,   // PKTCTRL0  Packet automation control.	//ɱ䳤�ݰ,ͨͬʻ�ĵ������ݰ�
    //0x00,   // ADDR      Device address.
	0x0A,   // ADDR      Device address. // �ݰ�ʱʹ�ĵ�
    //0x0c    // PKTLEN    Packet length.
	0xFF    // PKTLEN    Packet length.	  255 bytes
};
 */
/*
const RF_SETTINGS rfSettings = {
	0x00,
    0x06,   // FSCTRL1   Frequency synthesizer control.
    0x00,   // FSCTRL0   Frequency synthesizer control.
    0x10,   // FREQ2     Frequency control word, high byte.
    0xA7,   // FREQ1     Frequency control word, middle byte.
    0x62,   // FREQ0     Frequency control word, low byte.
    0xF5,   // MDMCFG4   Modem configuration.
    0x83,   // MDMCFG3   Modem configuration.
    0x03,   // MDMCFG2   Modem configuration.
    0x22,   // MDMCFG1   Modem configuration.
    0xF8,   // MDMCFG0   Modem configuration.

    0x00,   // CHANNR    Channel number.
    0x15,   // DEVIATN   Modem deviation setting (when FSK modulation is enabled).
    0x56,   // FREND1    Front end RX configuration.
    0x10,   // FREND0    Front end RX configuration.
    0x18,   // MCSM0     Main Radio Control State Machine configuration.
    0x16,   // FOCCFG    Frequency Offset Compensation Configuration.
    0x6C,   // BSCFG     Bit synchronization Configuration.
    0x03,   // AGCCTRL2  AGC control.
    0x40,   // AGCCTRL1  AGC control.
    0x91,   // AGCCTRL0  AGC control.

    0xE9,   // FSCAL3    Frequency synthesizer calibration.
    0x2A,   // FSCAL2    Frequency synthesizer calibration.
    0x00,   // FSCAL1    Frequency synthesizer calibration.
    0x1F,   // FSCAL0    Frequency synthesizer calibration.
    0x59,   // FSTEST    Frequency synthesizer calibration.
    0x88,   // TEST2     Various test settings.
    0x31,   // TEST1     Various test settings.
    0x0B,   // TEST0     Various test settings.
    0x0B,   // IOCFG2    GDO2 output pin configuration.
    0x06,   // IOCFG0D   GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.

    0x04,   // PKTCTRL1  Packet automation control.
	//0x05,   // PKTCTRL1  Packet automation control.	//�� 
    0x45,   // PKTCTRL0  Packet automation control.	//ɱ䳤�ݰ,ͨͬʻ�ĵ������ݰ�
    //0x00,   // ADDR      Device address.
	0x0A,   // ADDR      Device address. // �ݰ�ʱʹ�ĵ�
    //0x0c    // PKTLEN    Packet length.
	0xFF    // PKTLEN    Packet length.	  255 bytes
};
*/
// PATABLE (0 dBm output power)
unsigned char PaTabel[8] = {0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60};
//unsigned char PaTabel[8] = {0xC0 ,0xC0 ,0xC0 ,0xC0 ,0xC0 ,0xC0 ,0xC0 ,0xC0};

void halWait(INT16U timeout) 
{
    do 
	{
		__udelay(5);
    } while (--timeout);
}

extern void __iomem *spi_addr_vir;
unsigned char SpiTxByte(unsigned char dat)
{
	s3c2410_gpio_setpin(CSN,0);
	while(!(ioread8(spi_addr_vir+S3C2410_SPSTA)&S3C2410_SPSTA_READY));
	iowrite8(dat,spi_addr_vir+S3C2410_SPTDAT);
	s3c2410_gpio_setpin(CSN,1);	
	return 0;
}

unsigned char SpiRxByte(void)
{
	unsigned char tmp;
	s3c2410_gpio_setpin(CSN,0);	
	while(!(ioread8(spi_addr_vir+S3C2410_SPSTA)&S3C2410_SPSTA_READY));
	iowrite8(0xff,spi_addr_vir+S3C2410_SPTDAT);
	__udelay(50);
	while(!(ioread8(spi_addr_vir+S3C2410_SPSTA)&S3C2410_SPSTA_READY));
	tmp=ioread8(spi_addr_vir+S3C2410_SPRDAT);	
	s3c2410_gpio_setpin(CSN,1);	
	return tmp;
}

void RESET_CC1100(void) 
{
	s3c2410_gpio_setpin(CSN,1);
	__udelay(10);
	s3c2410_gpio_setpin(CSN,0);	
	__udelay(10);
	s3c2410_gpio_setpin(CSN,1);
	__udelay(80);
    	SpiTxByte(CCxxx0_SRES); 		//д�λ��
	__udelay(510);
}

void halSpiWriteReg(unsigned char addr, unsigned char value) 
{
	SpiTxByte(addr);		//д�
	__udelay(20); 
 	SpiTxByte(value);		//��
}

void halSpiWriteBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count) 
{
	unsigned char i, temp;
	temp = addr | WRITE_BURST;
	SpiTxByte(temp);
	__udelay(20);
	 for (i = 0; i < count; i++)
 	{
        	SpiTxByte(buffer[i]);
    	}
}

void halSpiStrobe(unsigned char strobe) 
{
    	SpiTxByte(strobe);		//��
}

unsigned char halSpiReadReg(unsigned char addr) 
{
	unsigned char temp, value;
    	temp = addr|READ_SINGLE;//|Ĵ���
	SpiTxByte(temp);
	__udelay(20);
	value = SpiRxByte();
	return value;
}

void halSpiReadBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count) 
{
    	unsigned char i,temp;
	temp = addr | READ_BURST;		//д�Ҫu��üĴ��ַͶ��
	SpiTxByte(temp);
	__udelay(10);
	for (i = 0; i < count; i++) 
	{
        	buffer[i] = SpiRxByte();
    	}
}

unsigned char halSpiReadStatus(unsigned char addr) 
{
    unsigned char value,temp;
	temp = addr | READ_BURST;		//д�Ҫu�̬Ĵ���ͬʱд���
    	SpiTxByte(temp);
	__udelay(10);
	value = SpiRxByte();
	return value;
}

void halRfWriteRfSettings(void) 
{

	halSpiWriteReg(CCxxx0_FSCTRL0,  rfSettings.FSCTRL2);
    	halSpiWriteReg(CCxxx0_FSCTRL1,  rfSettings.FSCTRL1);
    	halSpiWriteReg(CCxxx0_FSCTRL0,  rfSettings.FSCTRL0);
    	halSpiWriteReg(CCxxx0_FREQ2,    rfSettings.FREQ2);
    	halSpiWriteReg(CCxxx0_FREQ1,    rfSettings.FREQ1);
    	halSpiWriteReg(CCxxx0_FREQ0,    rfSettings.FREQ0);
    	halSpiWriteReg(CCxxx0_MDMCFG4,  rfSettings.MDMCFG4);
    	halSpiWriteReg(CCxxx0_MDMCFG3,  rfSettings.MDMCFG3);
    	halSpiWriteReg(CCxxx0_MDMCFG2,  rfSettings.MDMCFG2);
    	halSpiWriteReg(CCxxx0_MDMCFG1,  rfSettings.MDMCFG1);
    	halSpiWriteReg(CCxxx0_MDMCFG0,  rfSettings.MDMCFG0);
    	halSpiWriteReg(CCxxx0_CHANNR,   rfSettings.CHANNR);
    	halSpiWriteReg(CCxxx0_DEVIATN,  rfSettings.DEVIATN);
    	halSpiWriteReg(CCxxx0_FREND1,   rfSettings.FREND1);
    	halSpiWriteReg(CCxxx0_FREND0,   rfSettings.FREND0);
    	halSpiWriteReg(CCxxx0_MCSM0 ,   rfSettings.MCSM0 );
    	halSpiWriteReg(CCxxx0_FOCCFG,   rfSettings.FOCCFG);
    	halSpiWriteReg(CCxxx0_BSCFG,    rfSettings.BSCFG);
    	halSpiWriteReg(CCxxx0_AGCCTRL2, rfSettings.AGCCTRL2);
	halSpiWriteReg(CCxxx0_AGCCTRL1, rfSettings.AGCCTRL1);
    	halSpiWriteReg(CCxxx0_AGCCTRL0, rfSettings.AGCCTRL0);
    	halSpiWriteReg(CCxxx0_FSCAL3,   rfSettings.FSCAL3);
	halSpiWriteReg(CCxxx0_FSCAL2,   rfSettings.FSCAL2);
	halSpiWriteReg(CCxxx0_FSCAL1,   rfSettings.FSCAL1);
    	halSpiWriteReg(CCxxx0_FSCAL0,   rfSettings.FSCAL0);
    	halSpiWriteReg(CCxxx0_FSTEST,   rfSettings.FSTEST);
    	halSpiWriteReg(CCxxx0_TEST2,    rfSettings.TEST2);
    	halSpiWriteReg(CCxxx0_TEST1,    rfSettings.TEST1);
    	halSpiWriteReg(CCxxx0_TEST0,    rfSettings.TEST0);
    	halSpiWriteReg(CCxxx0_IOCFG2,   rfSettings.IOCFG2);
    	halSpiWriteReg(CCxxx0_IOCFG0,   rfSettings.IOCFG0);    
    	halSpiWriteReg(CCxxx0_PKTCTRL1, rfSettings.PKTCTRL1);
    	halSpiWriteReg(CCxxx0_PKTCTRL0, rfSettings.PKTCTRL0);
    	halSpiWriteReg(CCxxx0_ADDR,     rfSettings.ADDR);
    	halSpiWriteReg(CCxxx0_PKTLEN,   rfSettings.PKTLEN);
}


void halRfSendPacket(unsigned char *txBuffer, unsigned char size) 
{
	halSpiWriteReg(CCxxx0_TXFIFO, size);
    	halSpiWriteBurstReg(CCxxx0_TXFIFO, txBuffer, size);	//д�Ҫ���
    	halSpiStrobe(CCxxx0_STX);		//��ģʽ���
    // Wait for GDO0 to be set -> sync transmitted
   	while (!s3c2410_gpio_getpin(GDO0));
    // Wait for GDO0 to be cleared -> end of packet
    	while (s3c2410_gpio_getpin(GDO0));
	halSpiStrobe(CCxxx0_SFTX);
	printk("Figo5!\n");
}

void setRxMode(void)
{
    	halSpiStrobe(CCxxx0_SRX);		//���̬
}

unsigned char halRfReceivePacket(unsigned char *rxBuffer, unsigned char *length) 
{
  	unsigned char status[2];
   	unsigned char packetLength;
	 
   	if ((halSpiReadStatus(CCxxx0_RXBYTES) & BYTES_IN_RXFIFO)) //�ӵ�ֽ�Ϊ0
	{
       	packetLength = halSpiReadReg(CCxxx0_RXFIFO);//s�һ�ֽڣ�ֽ���ݳ�
       	if (packetLength <= *length) 		//��Ҫ���ݳ���ڽ�յ�ݰij�
		{
            		halSpiReadBurstReg(CCxxx0_RXFIFO, rxBuffer, packetLength); //s���յ��
            		*length = packetLength;				//ѽ��ݳȵ�޸�ǰ�ݵij�
        	         // Read the 2 appended status bytes (status[0] = RSSI, status[1] = LQI)
            		halSpiReadBurstReg(CCxxx0_RXFIFO, status, 2); 	//s�RCУ�λ
			halSpiStrobe(CCxxx0_SFRX);		//�ϴ�ջ�
            		return (status[1] & CRC_OK);			//�У�ɹؽ�ճɹ
       	}
        else 
		{
            		*length = packetLength;
            		halSpiStrobe(CCxxx0_SFRX);		//�ϴ�ջ�
            		return 0;
       	}
    } 
	else
 		return 0;
}