ml505.8

xilinx_v5sx95t_schematics(xilinx v5 95t 开发板原理图)

V 51
K 286873603900 ml401
Y 0
D 0 0 1700 1100
Z 1
i 809
N 803
J 360 670 2
J 360 660 2
S 2 1
N 684
J 480 920 3
J 250 920 1
J 480 930 5
J 420 930 2
J 530 930 2
S 1 3
S 2 1
L 260 920 10 0 3 0 1 0 PLAT_FLASH_CF_B
S 4 3
S 3 5
N 793
J 380 930 2
J 250 930 1
S 2 1
L 259 930 10 0 3 0 1 0 FPGA_PROG_B
N 466
J 620 100 2
J 630 100 3
J 630 110 5
J 620 110 2
J 620 130 2
J 620 120 2
J 630 120 5
J 630 130 5
J 630 140 5
J 620 140 2
J 620 150 2
J 630 150 5
J 620 160 2
J 630 160 5
J 620 170 2
J 630 170 5
J 630 180 2
S 1 2
S 2 3
S 3 7
S 4 3
S 16 17
S 15 16
S 14 16
S 13 14
S 12 14
S 11 12
S 9 12
S 10 9
S 8 9
S 6 7
S 5 8
S 7 8
N 563
J 520 160 2
J 410 160 1
S 2 1
L 420 170 10 6 3 0 1 0 CFG_ADDR_IN1
N 469
J 410 140 1
J 520 140 2
S 1 2
L 420 150 10 6 3 0 1 0 FPGA_M2
N 499
J 770 100 2
J 790 120 2
J 770 120 3
S 3 2
S 1 3
N 504
J 980 220 2
J 980 195 2
J 980 205 5
J 940 160 2
J 950 160 3
J 950 205 3
S 5 6
S 4 5
S 6 3
S 2 3
S 3 1
N 547
J 980 165 2
J 980 155 2
S 2 1
N 468
J 410 130 1
J 520 130 2
S 1 2
L 420 140 10 6 3 0 1 0 FPGA_M1
N 689
J 520 100 2
J 410 100 1
S 2 1
L 420 110 10 6 3 0 1 0 SYSACE_CFG_EN
N 509
J 790 160 2
J 690 160 1
S 2 1
L 700 160 10 0 3 0 1 0 SRAM_FLASH_D0_EN
N 508
J 790 140 2
J 691 140 1
S 2 1
L 700 140 10 0 3 0 1 0 FPGA_DIN
N 539
J 940 120 2
J 1030 120 1
S 1 2
L 960 120 10 0 3 0 1 0 SRAM_FLASH_D0
N 467
J 410 120 1
J 520 120 2
S 1 2
L 420 130 10 6 3 0 1 0 FPGA_M0
N 690
J 520 110 2
J 410 110 1
S 2 1
L 420 120 10 6 3 0 1 0 FPGA_FALLBACK_EN
N 745
J 530 410 2
J 250 410 1
S 2 1
L 260 410 10 0 3 0 1 0 PC4_TMS
N 743
J 250 420 1
J 530 420 2
S 1 2
L 260 420 10 0 3 0 1 0 PC4_TCK
N 777
J 380 490 2
J 250 490 1
S 2 1
L 260 490 10 0 3 0 1 0 PLAT_FLASH_CE2_B
N 741
J 250 510 1
J 530 510 2
S 1 2
L 259 510 10 0 3 0 1 0 FPGA_INIT_B
N 657
J 250 770 1
J 530 770 2
S 1 2
L 260 770 10 0 3 0 1 0 PLAT_FLASH1_TDO
N 655
J 250 780 1
J 530 780 2
S 1 2
L 260 780 10 0 3 0 1 0 PC4_TMS
N 653
J 530 790 2
J 250 790 1
S 2 1
L 260 790 10 0 3 0 1 0 PC4_TCK
N 656
J 530 800 2
J 250 800 1
S 2 1
L 260 800 10 0 3 0 1 0 PC4_TDI
N 630
J 530 860 2
J 250 860 1
S 2 1
L 260 860 10 0 3 0 1 0 PLAT_FLASH_CE_B
N 489
J 530 880 2
J 250 880 1
S 2 1
L 259 880 10 0 3 0 1 0 FPGA_INIT_B
N 490
J 530 890 2
J 250 890 1
S 2 1
L 260 890 10 0 3 0 1 0 PLAT_FLASH_CE2_B
N 503
J 360 980 2
J 530 870 2
J 250 900 1
J 360 760 2
J 360 900 5
J 360 870 5
J 380 900 2
S 5 1
S 3 5
L 260 900 10 0 3 0 1 0 FPGA_CCLK
S 5 7
S 6 5
S 4 6
S 6 2
N 562
J 250 950 1
J 380 950 2
S 1 2
L 259 950 10 0 3 0 1 0 FPGA_DOUT_BUSY
N 783
J 180 530 2
J 190 560 2
J 190 530 2
J 190 550 5
J 180 550 5
J 100 550 3
J 100 530 2
S 1 5
S 4 2
S 3 4
S 5 4
S 6 5
S 7 6
N 784
J 160 530 2
J 170 530 2
J 170 540 3
J 160 540 5
J 90 530 2
J 90 540 5
J 70 560 2
J 70 530 2
J 70 540 5
J 80 540 5
J 80 530 2
S 1 4
S 2 3
S 4 3
S 6 4
S 5 6
S 10 6
S 9 7
S 8 9
S 9 10
S 11 10
I 785 dxdesigner_lib:CPACK-4 1 110 470 1 1 '
|R 20:06_10-11-05
A 65 480 10 1 3 3 REFDES=CP12
A 120 470 10 1 3 0 PART_TYPE=CPACK
A 115 480 10 1 3 3 VALUE=0.1UF
A 135 480 10 1 3 3 VOLTAGE=10V
A 130 470 10 1 3 0 TOLERANCE=20%
A 125 480 10 1 3 3 DIELECTRIC=X5R
A 140 470 10 1 3 0 PKG_TYPE=0805-A4
A 150 470 10 1 3 0 DATASHEET=\\FENPHEN\AFX\AFX\BOARD_PROJECTS\LIBRARY\DATASHEETS
+ \CAPACITOR\PANA_ECJ_TVC1087.PDF
A 160 470 10 1 3 0 ROHS=
A 170 470 10 1 3 0 MANF=PANASONIC - ECG
A 180 470 10 1 3 0 MANF_P/N=P12977TR-ND
A 190 470 10 1 3 0 DIST=DIGI-KEY
A 200 470 10 1 3 0 DIST_P/N=P12977CT-ND
A 210 470 10 1 3 0 PRICE=0.102
A 130 490 10 1 3 0 DEVICE=0_1UF_0805
A 220 470 10 1 3 0 DXDB_LIBNAME=CAPACITORS
C 789 8 17 0
A 70 470 5 1 3 3 #=1
C 789 7 25 0
A 80 470 5 1 3 3 #=2
C 789 12 26 0
A 90 470 5 1 3 3 #=3
C 789 14 27 0
A 100 470 5 1 3 3 #=4
C 783 7 28 0
A 100 530 5 3 3 3 #=5
C 784 5 29 0
A 90 530 5 3 3 3 #=6
C 784 11 30 0
A 80 530 5 3 3 3 #=7
C 784 8 31 0
A 70 530 5 3 3 3 #=8
I 786 dxdesigner_lib:CPACK-4 1 200 470 1 1 '
|R 20:06_10-11-05
A 310 470 10 1 3 0 DXDB_LIBNAME=CAPACITORS
A 220 490 10 1 3 0 DEVICE=0_1UF_0805
A 300 470 10 1 3 0 PRICE=0.102
A 290 470 10 1 3 0 DIST_P/N=P12977CT-ND
A 280 470 10 1 3 0 DIST=DIGI-KEY
A 270 470 10 1 3 0 MANF_P/N=P12977TR-ND
A 260 470 10 1 3 0 MANF=PANASONIC - ECG
A 250 470 10 1 3 0 ROHS=
A 240 470 10 1 3 0 DATASHEET=\\FENPHEN\AFX\AFX\BOARD_PROJECTS\LIBRARY\DATASHEETS
+ \CAPACITOR\PANA_ECJ_TVC1087.PDF
A 230 470 10 1 3 0 PKG_TYPE=0805-A4
A 215 480 10 1 3 3 DIELECTRIC=X5R
A 220 470 10 1 3 0 TOLERANCE=20%
A 225 480 10 1 3 3 VOLTAGE=10V
A 205 480 10 1 3 3 VALUE=0.1UF
A 210 470 10 1 3 0 PART_TYPE=CPACK
A 155 480 10 1 3 3 REFDES=CP13
C 784 1 31 0
A 160 530 5 3 3 3 #=8
C 784 2 30 0
A 170 530 5 3 3 3 #=7
C 783 1 29 0
A 180 530 5 3 3 3 #=6
C 783 3 28 0
A 190 530 5 3 3 3 #=5
C 789 1 27 0
A 190 470 5 1 3 3 #=4
C 789 3 26 0
A 180 470 5 1 3 3 #=3
C 789 5 25 0
A 170 470 5 1 3 3 #=2
C 789 17 17 0
A 160 470 5 1 3 3 #=1
I 787 dxdesigner_lib:GND 1 60 420 0 1 '
|R 22:19_10-7-05
A 35 410 10 0 3 0 NETNAME=GND
C 789 9 1 0
I 788 schematics:VCC3V3 1 60 560 0 1 '
|R 22:50_2-28-06
C 784 7 2 0
N 789
J 190 470 2
J 190 460 3
J 180 470 2
J 180 460 5
J 170 470 2
J 170 460 5
J 80 470 2
J 70 470 2
J 70 440 2
J 70 460 5
J 80 460 5
J 90 470 2
J 90 460 5
J 100 470 2
J 100 460 5
J 160 460 5
J 160 470 2
S 2 1
S 4 2
S 4 3
S 6 4
S 6 5
S 16 6
S 11 7
S 10 8
S 9 10
S 10 11
S 11 13
S 13 12
S 13 15
S 15 14
S 15 16
S 16 17
I 790 dxdesigner_lib:VCC1V8 1 180 560 0 1 '
|R 17:26_3-2-06
C 783 2 2 0
N 780
J 530 900 2
J 410 900 2
S 2 1
L 421 900 7 0 3 0 1 0 PROM_CCLK-R
N 530
J 420 950 2
J 480 950 3
J 480 940 3
J 530 940 2
S 1 2
L 420 950 7 0 3 0 1 0 FPGA_DOUT_BUSY-R
S 3 4
S 3 2
N 720
J 891 370 2
J 871 440 2
J 891 440 5
J 871 490 2
J 891 490 5
J 891 590 3
J 871 590 2
S 1 3
S 2 3
S 3 5
S 4 5
S 5 6
S 7 6
N 722
J 900 620 2
J 900 470 3
J 871 470 2
S 2 1
S 3 2
I 723 schematics:VCC3V3 1 871 630 0 1 '
|R 22:50_2-28-06
C 753 9 2 0
N 733
J 470 520 1
J 530 520 2
S 1 2
A 479 520 10 0 3 1 NC
N 734
J 470 590 1
J 530 590 2
S 1 2
A 479 590 10 0 3 1 NC
N 735
J 530 610 2
J 470 610 1
S 2 1
A 479 610 10 0 3 1 NC
N 736
J 530 540 2
J 530 380 2
J 521 380 3
J 521 540 5
J 521 620 3
J 531 620 3
J 531 630 2
S 4 1
S 3 2
S 3 4
S 4 5
S 5 6
S 6 7
N 737
J 511 380 2
J 530 600 2
J 511 600 3
J 530 550 2
J 511 550 5
J 530 450 2
J 511 450 5
J 511 390 5
J 530 390 2
S 1 8
S 3 2
S 5 3
S 5 4
S 7 5
S 7 6
S 8 7
S 8 9
I 738 schematics:VCC3V3 1 521 630 0 1 '
|R 22:50_2-28-06
C 736 7 2 0
I 752 dxdesigner_lib:VCC1V8 1 491 650 0 1 '
|R 17:26_3-2-06
C 755 1 2 0
N 753
J 871 430 2
J 881 430 3
J 871 510 2
J 870 510 3
J 881 510 5
J 871 580 2
J 870 580 3
J 881 580 5
J 881 630 2
S 1 2
S 2 5
S 4 3
S 4 5
S 5 8
S 7 6
S 7 8
S 8 9
I 754 dxdesigner_lib:GND 1 881 350 0 1 '
|R 22:19_10-7-05
A 856 340 10 0 3 0 NETNAME=GND
C 720 1 1 0
N 755
J 501 650 2
J 530 580 2
J 501 580 5
J 501 470 3
J 530 470 2
S 3 1
S 3 2
S 4 3
S 4 5
I 756 dxdesigner_lib:GND 1 501 360 0 1 '
|R 22:19_10-7-05
A 476 350 10 0 3 0 NETNAME=GND
C 737 1 1 0
N 757
J 530 440 2
J 470 440 1
S 2 1
A 479 440 10 0 3 1 NC
N 758
J 470 460 1
J 530 460 2
S 1 2
A 479 460 10 0 3 1 NC
N 759
J 530 480 2
J 470 480 1
S 2 1
A 479 480 10 0 3 1 NC
N 760
J 871 480 2
J 955 480 1
S 1 2
A 925 480 10 0 3 1 NC
N 761
J 955 500 1
J 871 500 2
S 2 1
A 925 500 10 0 3 1 NC
N 762
J 871 520 2
J 955 520 1
S 1 2
A 925 520 10 0 3 1 NC
N 763
J 955 530 1
J 871 530 2
S 2 1
A 925 530 10 0 3 1 NC
N 764
J 871 540 2
J 955 540 1
S 1 2
A 925 540 10 0 3 1 NC
N 765
J 955 550 1
J 871 550 2
S 2 1
A 925 550 10 0 3 1 NC
I 770 dxdesigner_lib:VCC1V8 1 890 620 0 1 '
|R 17:26_3-2-06
C 722 1 2 0
I 709 dxdesigner_lib:VCC1V8 1 180 930 0 1 '
|R 17:26_3-2-06
C 610 7 2 0
N 696
J 1430 370 2
J 1430 380 2
S 1 2
I 697 dxdesigner_lib:GND 1 1420 350 0 1 '
|R 22:19_10-7-05
A 1395 340 10 0 3 0 NETNAME=GND
C 696 1 1 0
N 695
J 1350 410 3
J 1350 425 5
J 1350 510 3
J 1430 510 5
J 1430 520 2
J 1430 500 2
J 1360 425 2
J 1360 410 2
S 1 8
S 2 7
S 3 4
S 2 3
S 6 4
S 4 5
S 1 2
I 692 dxdesigner_lib:VCC1V8 1 890 990 0 1 '
|R 17:26_3-2-06
C 544 3 2 0
N 531
J 871 920 2
J 955 920 1
S 1 2
A 925 920 10 0 3 1 NC
N 532
J 955 910 1
J 871 910 2
S 2 1
A 925 910 10 0 3 1 NC
N 533
J 871 900 2
J 955 900 1
S 1 2
A 925 900 10 0 3 1 NC
N 534
J 955 890 1
J 871 890 2
S 2 1
A 925 890 10 0 3 1 NC
N 535
J 871 870 2
J 955 870 1
S 1 2
A 925 870 10 0 3 1 NC
N 536
J 955 850 1
J 871 850 2
S 2 1
A 925 850 10 0 3 1 NC
N 516
J 470 810 1
J 530 810 2
S 1 2
A 479 810 10 0 3 1 NC
N 603
J 1260 980 2
J 1260 990 2
S 1 2
N 602
J 1260 1030 2
J 1260 1020 2
S 2 1
N 588
J 1450 670 2
J 1390 670 3
J 1390 680 2
S 2 1
S 2 3
N 589
J 1430 660 2
J 1430 690 3
J 1450 690 2
S 1 2
S 2 3
I 596 schematics:VCC3V3 1 1380 680 0 1 '
|R 22:50_2-28-06
C 588 3 2 0
I 465 schematics:VCC3V3 1 640 180 4 1 '
|R 22:50_2-28-06
C 466 17 2 0
I 500 dxdesigner_lib:GND 1 760 80 0 1 '
|R 22:19_10-7-05
A 735 70 10 0 3 0 NETNAME=GND
C 499 1 1 0
N 501
J 1560 960 1
J 1510 960 2
S 2 1
A 1530 960 10 0 3 1 NC
N 502
J 1330 960 1
J 1370 960 2
S 1 2
A 1340 960 10 0 3 1 NC
I 505 schematics:VCC3V3 1 970 220 0 1 '
|R 22:50_2-28-06
C 504 1 2 0
I 506 dxdesigner_lib:GND 1 970 135 0 1 '
|R 22:19_10-7-05
A 945 125 10 0 3 0 NETNAME=GND
C 547 2 1 0
N 526
J 530 840 2
J 501 840 3
J 530 950 2
J 501 950 5
J 501 1020 2
S 2 1
S 2 4
S 4 3
S 4 5
I 538 dxdesigner_lib:GND 1 881 720 0 1 '
|R 22:19_10-7-05
A 856 710 10 0 3 0 NETNAME=GND
C 537 5 1 0
N 541
J 881 1000 2
J 881 950 5
J 871 950 2
J 870 950 3
J 871 880 2
J 870 880 3
J 871 800 2
J 881 800 3
J 881 880 5
S 2 1
S 4 3
S 4 2
S 6 5
S 6 9
S 7 8
S 8 9
S 9 2
N 548
J 1370 950 2
J 1330 950 1
S 2 1
A 1340 950 10 0 3 1 NC
N 549
J 1330 940 1
J 1370 940 2
S 1 2
A 1340 940 10 0 3 1 NC
N 550
J 1370 930 2
J 1330 930 1
S 2 1
A 1340 930 10 0 3 1 NC
N 552
J 1510 950 2