variable_counter.v

写给小白们的FPGA入门设计实验

/*-------------------------------------------------------------------------
CONFIDENTIAL IN CONFIDENCE
This confidential and proprietary software may be only used as authorized
by a licensing agreement from CrazyBingo (Thereturnofbingo).
In the event of publication, the following notice is applicable:
Copyright (C) 2011-2012 CrazyBingo Corporation
The entire notice above must be reproduced on all authorized copies.
Author				:		CrazyBingo
Technology blogs 	: 		http://blog.chinaaet.com/crazybingo
							http://www.cnblogs.com/crazybingo
Eamil Address 		: 		[e-mail]
Filename			:		variable_counter.v
Data				:		2012-11-01
Version				:		1.0
Description			:		a counter with variable max data.
Modification History	:
Data			By			Version			Change Description
===========================================================================
12/11/01		CrazyBingo	1.0				Original
--------------------------------------------------------------------------*/
module	variable_counter
(
	input	clk,
	input	rst_n,
	
	input	key_index,
	output	[6:0]	oSEG0,	//ge_data
	output	[6:0]	oSEG1	//shi_data
);
wire	[7:0]	max_vaule = key_index ? 8'd64 : 8'd16;

//----------------------------
reg	[23:0]	cnt;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		cnt <= 0;
	else
		cnt <= (cnt == 24'd12500000) ? 24'd0 : cnt + 1'b1;
end
wire	delay02_flag = (cnt == 24'd12500000) ? 1'b1 : 1'b0;	//0.2s flag

//-------------------------------
//data counter
reg	[7:0]	counter;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		counter <= 0;
	else if(delay02_flag)
		counter <= (counter >= max_vaule) ? 8'd0 : counter + 1'b1;
end

//-------------------------------
//hex2decimal convert
wire	[3:0]	shi_data = 	(counter < 10)? 4'd0:
							(counter < 20)?	4'd1:
							(counter < 30)?	4'd2:
							(counter < 40)? 4'd3:
							(counter < 50)? 4'd4:
							(counter < 60)? 4'd5:
							(counter < 70)? 4'd6:
							(counter < 80)? 4'd7:
							(counter < 90)? 4'd8:	
							4'd9;

wire	[3:0]	ge_data = 	(counter < 10)? counter - 8'd0:
							(counter < 20)?	counter - 8'd10:
							(counter < 30)?	counter - 8'd20:
							(counter < 40)? counter - 8'd30:
							(counter < 50)? counter - 8'd40:
							(counter < 60)? counter - 8'd50:
							(counter < 70)? counter - 8'd60:
							(counter < 80)? counter - 8'd70:
							(counter < 90)? counter - 8'd80:	
							counter - 8'd90;

//shi_data display							
Seg7_lut u_Seg7_lut1	
(	
	.iDIG	(shi_data),
	.oSEG	(oSEG1)
);

//ge_data display
Seg7_lut u_Seg7_lut2	
(	
	.iDIG	(ge_data),
	.oSEG	(oSEG0)
);
endmodule