sequence_detect.v

来自「写给小白们的FPGA入门设计实验」· Verilog 代码 · 共 68 行

/*-------------------------------------------------------------------------
CONFIDENTIAL IN CONFIDENCE
This confidential and proprietary software may be only used as authorized
by a licensing agreement from CrazyBingo (Thereturnofbingo).
In the event of publication, the following notice is applicable:
Copyright (C) 2011-2012 CrazyBingo Corporation
The entire notice above must be reproduced on all authorized copies.
Author				:		CrazyBingo
Technology blogs 	: 		http://blog.chinaaet.com/crazybingo
							http://www.cnblogs.com/crazybingo
Eamil Address 		: 		[e-mail]
Filename			:		sequence_detect.v
Data				:		2012-11-01
Version				:		1.0
Description			:		detect of data sequence for special.
Modification History	:
Data			By			Version			Change Description
===========================================================================
12/11/01		CrazyBingo	1.0				Original
--------------------------------------------------------------------------*/
`timescale 1 ns / 1 ns
module	sequence_detect
(
	input	clk,
	input	rst_n,
	
	input	din_en,	//H vaild
	input	din,
	output	reg	dout
);


//-------------------------------------------
//capture the posedge of din_en for data receive
reg	din_en_r0,din_en_r1;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		begin
		din_en_r0 <= 0;
		din_en_r1 <= 0;
		end
	else
		begin
		din_en_r0 <= din_en;
		din_en_r1 <= din_en_r0;
		end
end
wire	din_flag = (~din_en_r1 & din_en_r0) ? 1'b1 : 1'b0;

//--------------------------------------------
reg	[3:0]	sequence_data;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		begin
		sequence_data <= 0;
		dout <= 0;
		end
	else if(din_flag)
		begin
		sequence_data <= {sequence_data[2:0], din};
		dout <= (sequence_data == 4'b1111) ? 1'b1 : 1'b0;
		end
end

endmodule