operations_4.map.rpt

写给小白们的FPGA入门设计实验

+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ;   0.0%      ;
+----------------------------+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                            ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------------------------------+
; ../src/seg7_lut.v                ; yes             ; User Verilog HDL File  ; D:/Altera_Project/arithmetic_design/operations_4/src/seg7_lut.v         ;
; ../src/variable_counter.v        ; yes             ; User Verilog HDL File  ; D:/Altera_Project/arithmetic_design/operations_4/src/variable_counter.v ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 134   ;
;                                             ;       ;
; Total combinational functions               ; 134   ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 90    ;
;     -- 3 input functions                    ; 6     ;
;     -- <=2 input functions                  ; 38    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 104   ;
;     -- arithmetic mode                      ; 30    ;
;                                             ;       ;
; Total registers                             ; 32    ;
;     -- Dedicated logic registers            ; 32    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 17    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 32    ;
; Total fan-out                               ; 578   ;
; Average fan-out                             ; 3.16  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                            ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                    ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------+--------------+
; |variable_counter          ; 134 (119)         ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 17   ; 0            ; |variable_counter                      ; work         ;
;    |Seg7_lut:u_Seg7_lut1|  ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |variable_counter|Seg7_lut:u_Seg7_lut1 ;              ;
;    |Seg7_lut:u_Seg7_lut2|  ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |variable_counter|Seg7_lut:u_Seg7_lut2 ;              ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 32    ;
; Number of registers using Synchronous Clear  ; 8     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 32    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 8     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                              ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+
; 7:1                ; 2 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |variable_counter|shi_data[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Nov 01 21:26:10 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off operations_4 -c operations_4
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Found 1 design units, including 1 entities, in source file /altera_project/arithmetic_design/operations_4/src/seg7_lut.v
    Info: Found entity 1: Seg7_lut
Info: Found 1 design units, including 1 entities, in source file /altera_project/arithmetic_design/operations_4/src/adder_4bits.v
    Info: Found entity 1: adder_4bits
Info: Found 1 design units, including 1 entities, in source file /altera_project/arithmetic_design/operations_4/src/mult_3bits.v
    Info: Found entity 1: mult_3bits
Info: Found 1 design units, including 1 entities, in source file /altera_project/arithmetic_design/operations_4/src/operations_4.v
    Info: Found entity 1: operations_4
Info: Found 1 design units, including 1 entities, in source file /altera_project/arithmetic_design/operations_4/src/sequence_detect.v
    Info: Found entity 1: sequence_detect
Info: Found 1 design units, including 1 entities, in source file /altera_project/arithmetic_design/operations_4/src/subtractor_4bits.v
    Info: Found entity 1: subtractor_4bits
Info: Found 1 design units, including 1 entities, in source file /altera_project/arithmetic_design/operations_4/src/variable_counter.v
    Info: Found entity 1: variable_counter
Info: Elaborating entity "variable_counter" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at variable_counter.v(67): truncated value with size 8 to match size of target (4)
Info: Elaborating entity "Seg7_lut" for hierarchy "Seg7_lut:u_Seg7_lut1"
Info: Generated suppressed messages file D:/Altera_Project/arithmetic_design/operations_4/dev/operations_4.map.smsg
Info: Implemented 151 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 14 output pins
    Info: Implemented 134 logic cells
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 266 megabytes
    Info: Processing ended: Thu Nov 01 21:26:12 2012
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in D:/Altera_Project/arithmetic_design/operations_4/dev/operations_4.map.smsg.