time_counter.v

写给小白们的FPGA入门设计实验

/*-------------------------------------------------------------------------
CONFIDENTIAL IN CONFIDENCE
This confidential and proprietary software may be only used as authorized
by a licensing agreement from CrazyBingo (Thereturnofbingo).
In the event of publication, the following notice is applicable:
Copyright (C) 2011-2012 CrazyBingo Corporation
The entire notice above must be reproduced on all authorized copies.
Author				:		CrazyBingo
Technology blogs 	: 		http://blog.chinaaet.com/crazybingo
							http://www.cnblogs.com/crazybingo
Eamil Address 		: 		[e-mail]
Filename			:		time_counter.v
Data				:		2012-11-01
Version				:		1.0
Description			:		precise time counter design with fpga.
Modification History	:
Data			By			Version			Change Description
===========================================================================
12/11/01		CrazyBingo	1.0				Original
--------------------------------------------------------------------------*/
`timescale 1 ns / 1 ns
module time_counter
(
	input	clk,			//50MHz
	input	rst_n,
	
	output	[2:0]	min_h,	//minute
	output	[3:0]	min_l,
	output	[2:0]	sec_h,	//second
	output	[3:0]	sec_l,
	output	[3:0]	mse_h,	//microseconds
	output	[3:0]	mse_b,	
	output	[3:0]	mse_l	//1000Hz
);


//----------------------------
//1us delay
reg	[27:0]	cnt;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		cnt <= 0;
	else
		cnt <= (cnt >= 16'd49_999) ? 16'd0 : cnt + 1'b1;
end
wire	delay_1us = (cnt == 16'd49_999) ? 1'b1 : 1'b0;	//1us flag


//assign	min_h = 3'd5;
//assign	min_l = 4'd9;
//assign	sec_h = 3'd5;
//assign	sec_l = 4'd9;
//assign	mse_h = 4'd9;
//assign	mse_b = 4'd9;
//assign	mse_l = 4'd9;

reg	[6:0]	min;	//minute
reg	[6:0]	sec;	//secnod
reg	[9:0]	mse;	//microseconds
//------------------------------------------
//counter for min, sec, and mse
always@(posedge clk or  negedge rst_n)
begin
	if(!rst_n)
		begin
		min <= 0; sec <= 0; mse <= 0;
		end
	else
		begin
		if(delay_1us)
			begin
			if(min < 59)
				begin
				if(sec < 59)
					begin
					if(mse < 999)
						mse <= mse+1'b1;
					else
						begin
						mse <= 0;sec <= sec+1'b1;
						end
					end
				else		//sec=59
					begin
					if(mse < 999)
						mse <= mse+1'b1;
					else	//sec=59,mse=999
						begin
						mse <= 0;sec <= 0;min <= min+1'b1;
						end
					end
				end
			else
				begin
				if(sec < 59)
					begin
					if(mse < 999)
						mse  <= mse+1'b1;
					else
						begin
						mse <= 0;sec <= sec+1'b1;
						end
					end
				else	//sec=59
					begin
					if(mse < 999)
						mse <= mse+1'b1;
					else//mse=999,sec=59,min=59
						begin
						mse <= 0;sec <= 0;min <= 0;
						end
					end
				end
			end
		end
end

//-----------------------------------------------
//every bit of minute 
wire	[6:0]	min_r;
assign	min_h = (min < 10)? 3'd0:
				(min < 20)?	3'd1:
				(min < 30)?	3'd2:
				(min < 40)? 3'd3:
				(min < 50)? 3'd4:
							3'd5;
assign	min_r = (min < 10)? min-7'd0 : 
				(min < 20)? min-7'd10:
				(min < 30)? min-7'd20:
				(min < 40)? min-7'd30:
				(min < 50)? min-7'd40:
							min-7'd50;
assign	min_l = min_r[3:0];
								 
//-----------------------------------------------
//every bit of second 
wire	[6:0]	sec_r;
assign	sec_h = (sec < 10)? 3'd0:
				(sec < 20)?	3'd1:
				(sec < 30)?	3'd2:
				(sec < 40)? 3'd3:
				(sec < 50)? 3'd4:
							3'd5;							 
assign	sec_r = (sec< 10)? sec-7'd0 : 
				(sec< 20)? sec-7'd10:
				(sec< 30)? sec-7'd20:
				(sec< 40)? sec-7'd30:
				(sec< 50)? sec-7'd40:
						   sec-7'd50;
assign	sec_l = sec_r[3:0];

//-----------------------------------------------
//every bit of microseconds 
wire	[9:0]	mse_br;
wire	[9:0]	mse_lr;
assign	mse_h = (mse < 100)? 	4'd0:
				(mse < 200)?	4'd1:
				(mse < 300)?	4'd2:
				(mse < 400)? 	4'd3:
				(mse < 500)? 	4'd4:
				(mse < 600)? 	4'd5:
				(mse < 700)? 	4'd6:
				(mse < 800)? 	4'd7:
				(mse < 900)? 	4'd8:
								4'd9;
assign	mse_br = mse % 10'd100 / 4'd10;							 
assign	mse_lr = mse % 4'd10;
assign	mse_b = mse_br[3:0];
assign	mse_l = mse_lr[3:0];

endmodule