labtest.v

写给小白们的FPGA入门设计实验

/*-------------------------------------------------------------------------
CONFIDENTIAL IN CONFIDENCE
This confidential and proprietary software may be only used as authorized
by a licensing agreement from CrazyBingo (Thereturnofbingo).
In the event of publication, the following notice is applicable:
Copyright (C) 2011-2012 CrazyBingo Corporation
The entire notice above must be reproduced on all authorized copies.
Author				:		CrazyBingo
Technology blogs 	: 		http://blog.chinaaet.com/crazybingo
							http://www.cnblogs.com/crazybingo
Eamil Address 		: 		[e-mail]
Filename			:		time_counter.v
Data				:		2012-11-01
Version				:		1.0
Description			:		precise time counter design with fpga.
Modification History	:
Data			By			Version			Change Description
===========================================================================
12/11/01		CrazyBingo	1.0				Original
--------------------------------------------------------------------------*/
module	Labtest
(
	input	clk,
	input	rst_n,
	
	output	[6:0]	oSEG3,
	output	[6:0]	oSEG2,
	output	[6:0]	oSEG1,
	output	[6:0]	oSEG0
);

wire	[2:0]	min_h;
wire	[3:0]	min_l;
wire	[2:0]	sec_h;
wire	[3:0]	sec_l;
time_counter u_time_counter
(
	.clk		(clk),
	.rst_n		(rst_n),
	
	.min_h		(min_h),	//minute
	.min_l		(min_l),
	.sec_h		(sec_h),	//second
	.sec_l		(sec_l),
	.mse_h		(),			//microseconds
	.mse_b		(),	
	.mse_l		()			//1000Hz
);

//shi_data display							
Seg7_lut u_Seg7_lut3	
(	
	.iDIG	({1'b0, min_h}),
	.oSEG	(oSEG3)
);

//ge_data display
Seg7_lut u_Seg7_lut2	
(	
	.iDIG	(min_l),
	.oSEG	(oSEG2)
);

//shi_data display							
Seg7_lut u_Seg7_lut1	
(	
	.iDIG	({1'b0,sec_h}),
	.oSEG	(oSEG1)
);

//ge_data display
Seg7_lut u_Seg7_lut0
(	
	.iDIG	(sec_l),
	.oSEG	(oSEG0)
);

endmodule