led_display.v

来自「写给小白们的FPGA入门设计实验」· Verilog 代码 · 共 30 行

module	led_display

(
	input				clk,
	input				rst_n,
	
	output	reg	[7:0]	led_data
);

//----------------------------
reg	[27:0]	cnt;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		cnt <= 0;
	else
		cnt <= (cnt == 28'd150_000000) ? 28'd0 : cnt + 1'b1;
end
wire	delay03_flag = (cnt == 28'd150_000000) ? 1'b1 : 1'b0;	//3s flag

always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		led_data <= 0;
	else if(delay03_flag)
		led_data <= {led_data[6:0],1'b1};
end

endmodule