labtest.tan.rpt

写给小白们的FPGA入门设计实验

; Analyze latches as synchronous elements                                                              ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                                                     ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                                                 ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                                                        ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                                                    ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                                                    ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node                                                ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                                                                ; 10                 ;      ;    ;             ;
; Number of paths to report                                                                            ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                                                         ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                                                               ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                                                           ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                                                         ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis                                       ; Off                ;      ;    ;             ;
; Reports worst-case timing paths for each clock domain and analysis                                   ; On                 ;      ;    ;             ;
; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation                                  ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                                                           ; Near End           ;      ;    ;             ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ;   0.0%      ;
+----------------------------+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                   ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------+------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                ; To                                 ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------+------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 140.41 MHz ( period = 7.122 ns )                    ; time_counter:u_time_counter|cnt[17] ; time_counter:u_time_counter|sec[1] ; clk        ; clk      ; None                        ; None                      ; 6.849 ns                ;
; N/A                                     ; 140.41 MHz ( period = 7.122 ns )                    ; time_counter:u_time_counter|cnt[17] ; time_counter:u_time_counter|sec[2] ; clk        ; clk      ; None                        ; None                      ; 6.849 ns                ;
; N/A                                     ; 140.69 MHz ( period = 7.108 ns )                    ; time_counter:u_time_counter|cnt[17] ; time_counter:u_time_counter|min[0] ; clk        ; clk      ; None                        ; None                      ; 6.840 ns                ;
; N/A                                     ; 140.77 MHz ( period = 7.104 ns )                    ; time_counter:u_time_counter|cnt[17] ; time_counter:u_time_counter|sec[0] ; clk        ; clk      ; None                        ; None                      ; 6.831 ns                ;
; N/A                                     ; 140.86 MHz ( period = 7.099 ns )                    ; time_counter:u_time_counter|cnt[17] ; time_counter:u_time_counter|min[2] ; clk        ; clk      ; None                        ; None                      ; 6.831 ns                ;
; N/A                                     ; 140.86 MHz ( period = 7.099 ns )                    ; time_counter:u_time_counter|cnt[17] ; time_counter:u_time_counter|min[1] ; clk        ; clk      ; None                        ; None                      ; 6.831 ns                ;
; N/A                                     ; 142.55 MHz ( period = 7.015 ns )                    ; time_counter:u_time_counter|cnt[17] ; time_counter:u_time_counter|sec[6] ; clk        ; clk      ; None                        ; None                      ; 6.742 ns                ;
; N/A                                     ; 142.55 MHz ( period = 7.015 ns )                    ; time_counter:u_time_counter|cnt[17] ; time_counter:u_time_counter|sec[5] ; clk        ; clk      ; None                        ; None                      ; 6.742 ns                ;
; N/A                                     ; 142.65 MHz ( period = 7.010 ns )                    ; time_counter:u_time_counter|cnt[16] ; time_counter:u_time_counter|sec[1] ; clk        ; clk      ; None                        ; None                      ; 6.737 ns                ;
; N/A                                     ; 142.65 MHz ( period = 7.010 ns )                    ; time_counter:u_time_counter|cnt[16] ; time_counter:u_time_counter|sec[2] ; clk        ; clk      ; None                        ; None                      ; 6.737 ns                ;