labtest.fit.rpt

写给小白们的FPGA入门设计实验

; Optimize Hold Timing                                                       ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Multi-Corner Timing                                               ; Off                            ; Off                            ;
; PowerPlay Power Optimization                                               ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                            ; Normal compilation             ; Normal compilation             ;
; Optimize Timing for ECOs                                                   ; Off                            ; Off                            ;
; Regenerate full fit report during ECO compiles                             ; Off                            ; Off                            ;
; Optimize IOC Register Placement for Timing                                 ; On                             ; On                             ;
; Limit to One Fitting Attempt                                               ; Off                            ; Off                            ;
; Final Placement Optimizations                                              ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                                ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                              ; 1                              ; 1                              ;
; PCI I/O                                                                    ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                      ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                                  ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                         ; Off                            ; Off                            ;
; Auto Packed Registers                                                      ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                          ; On                             ; On                             ;
; Auto Merge PLLs                                                            ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                          ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                               ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                                ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                                  ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                     ; Off                            ; Off                            ;
; Fitter Effort                                                              ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                            ; Normal                         ; Normal                         ;
; Auto Global Clock                                                          ; On                             ; On                             ;
; Auto Global Register Control Signals                                       ; On                             ; On                             ;
; Stop After Congestion Map Generation                                       ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                          ; Off                            ; Off                            ;
; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                            ; Off                            ;
; Use Best Effort Settings for Compilation                                   ; Off                            ; Off                            ;
+----------------------------------------------------------------------------+--------------------------------+--------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.33        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ;  20.0%      ;
+----------------------------+-------------+


+----------------------------------------------+
; Incremental Compilation Preservation Summary ;
+-------------------------+--------------------+
; Type                    ; Value              ;
+-------------------------+--------------------+
; Placement               ;                    ;
;     -- Requested        ; 0 / 266 ( 0.00 % ) ;
;     -- Achieved         ; 0 / 266 ( 0.00 % ) ;
;                         ;                    ;
; Routing (by Connection) ;                    ;
;     -- Requested        ; 0 / 0 ( 0.00 % )   ;
;     -- Achieved         ; 0 / 0 ( 0.00 % )   ;
+-------------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings                                                                                                       ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
; Top            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;          ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+


+--------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation                                             ;
+----------------+---------+-------------------+-------------------------+-------------------+
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+----------------+---------+-------------------+-------------------------+-------------------+
; Top            ; 266     ; 0                 ; N/A                     ; Source File       ;
+----------------+---------+-------------------+-------------------------+-------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/Altera_Project/Labtest/Labtest.pin.


+----------------------------------------------------------------------+
; Fitter Resource Usage Summary                                        ;
+---------------------------------------------+------------------------+
; Resource                                    ; Usage                  ;
+---------------------------------------------+------------------------+
; Total logic elements                        ; 179 / 33,216 ( < 1 % ) ;
;     -- Combinational with no register       ; 127                    ;
;     -- Register only                        ; 0                      ;