prev_cmp_lcd1602_driver.tan.qmsg

写给小白们的FPGA入门设计实验

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[13\] register current_state.ROW2_F 296.21 MHz 3.376 ns Internal " "Info: Clock \"clk\" has Internal fmax of 296.21 MHz between source register \"cnt\[13\]\" and destination register \"current_state.ROW2_F\" (period= 3.376 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.158 ns + Longest register register " "Info: + Longest register to register delay is 3.158 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[13\] 1 REG LCFF_X7_Y27_N25 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X7_Y27_N25; Fanout = 3; REG Node = 'cnt\[13\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { cnt[13] } "NODE_NAME" } } { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.737 ns) + CELL(0.410 ns) 1.147 ns Equal0~3 2 COMB LCCOMB_X6_Y27_N20 1 " "Info: 2: + IC(0.737 ns) + CELL(0.410 ns) = 1.147 ns; Loc. = LCCOMB_X6_Y27_N20; Fanout = 1; COMB Node = 'Equal0~3'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.147 ns" { cnt[13] Equal0~3 } "NODE_NAME" } } { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.276 ns) + CELL(0.410 ns) 1.833 ns Equal0~4 3 COMB LCCOMB_X6_Y27_N26 49 " "Info: 3: + IC(0.276 ns) + CELL(0.410 ns) = 1.833 ns; Loc. = LCCOMB_X6_Y27_N26; Fanout = 49; COMB Node = 'Equal0~4'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.686 ns" { Equal0~3 Equal0~4 } "NODE_NAME" } } { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.665 ns) + CELL(0.660 ns) 3.158 ns current_state.ROW2_F 4 REG LCFF_X4_Y27_N25 4 " "Info: 4: + IC(0.665 ns) + CELL(0.660 ns) = 3.158 ns; Loc. = LCFF_X4_Y27_N25; Fanout = 4; REG Node = 'current_state.ROW2_F'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.325 ns" { Equal0~4 current_state.ROW2_F } "NODE_NAME" } } { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.480 ns ( 46.87 % ) " "Info: Total cell delay = 1.480 ns ( 46.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.678 ns ( 53.13 % ) " "Info: Total interconnect delay = 1.678 ns ( 53.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "3.158 ns" { cnt[13] Equal0~3 Equal0~4 current_state.ROW2_F } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "3.158 ns" { cnt[13] {} Equal0~3 {} Equal0~4 {} current_state.ROW2_F {} } { 0.000ns 0.737ns 0.276ns 0.665ns } { 0.000ns 0.410ns 0.410ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.004 ns - Smallest " "Info: - Smallest clock skew is -0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.644 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.644 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 65 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 65; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.537 ns) 2.644 ns current_state.ROW2_F 3 REG LCFF_X4_Y27_N25 4 " "Info: 3: + IC(0.990 ns) + CELL(0.537 ns) = 2.644 ns; Loc. = LCFF_X4_Y27_N25; Fanout = 4; REG Node = 'current_state.ROW2_F'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.527 ns" { clk~clkctrl current_state.ROW2_F } "NODE_NAME" } } { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 58.09 % ) " "Info: Total cell delay = 1.536 ns ( 58.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.108 ns ( 41.91 % ) " "Info: Total interconnect delay = 1.108 ns ( 41.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "2.644 ns" { clk clk~clkctrl current_state.ROW2_F } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "2.644 ns" { clk {} clk~combout {} clk~clkctrl {} current_state.ROW2_F {} } { 0.000ns 0.000ns 0.118ns 0.990ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.648 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.648 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 65 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 65; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.537 ns) 2.648 ns cnt\[13\] 3 REG LCFF_X7_Y27_N25 3 " "Info: 3: + IC(0.994 ns) + CELL(0.537 ns) = 2.648 ns; Loc. = LCFF_X7_Y27_N25; Fanout = 3; REG Node = 'cnt\[13\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.531 ns" { clk~clkctrl cnt[13] } "NODE_NAME" } } { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 58.01 % ) " "Info: Total cell delay = 1.536 ns ( 58.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.112 ns ( 41.99 % ) " "Info: Total interconnect delay = 1.112 ns ( 41.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "2.648 ns" { clk clk~clkctrl cnt[13] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "2.648 ns" { clk {} clk~combout {} clk~clkctrl {} cnt[13] {} } { 0.000ns 0.000ns 0.118ns 0.994ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "2.644 ns" { clk clk~clkctrl current_state.ROW2_F } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "2.644 ns" { clk {} clk~combout {} clk~clkctrl {} current_state.ROW2_F {} } { 0.000ns 0.000ns 0.118ns 0.990ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "2.648 ns" { clk clk~clkctrl cnt[13] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "2.648 ns" { clk {} clk~combout {} clk~clkctrl {} cnt[13] {} } { 0.000ns 0.000ns 0.118ns 0.994ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 91 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "3.158 ns" { cnt[13] Equal0~3 Equal0~4 current_state.ROW2_F } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "3.158 ns" { cnt[13] {} Equal0~3 {} Equal0~4 {} current_state.ROW2_F {} } { 0.000ns 0.737ns 0.276ns 0.665ns } { 0.000ns 0.410ns 0.410ns 0.660ns } "" } } { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "2.644 ns" { clk clk~clkctrl current_state.ROW2_F } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "2.644 ns" { clk {} clk~combout {} clk~clkctrl {} current_state.ROW2_F {} } { 0.000ns 0.000ns 0.118ns 0.990ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "2.648 ns" { clk clk~clkctrl cnt[13] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "2.648 ns" { clk {} clk~combout {} clk~clkctrl {} cnt[13] {} } { 0.000ns 0.000ns 0.118ns 0.994ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk lcd_en cnt\[15\] 6.775 ns register " "Info: tco from clock \"clk\" to destination pin \"lcd_en\" through register \"cnt\[15\]\" is 6.775 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.648 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.648 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 65 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 65; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.537 ns) 2.648 ns cnt\[15\] 3 REG LCFF_X7_Y27_N29 3 " "Info: 3: + IC(0.994 ns) + CELL(0.537 ns) = 2.648 ns; Loc. = LCFF_X7_Y27_N29; Fanout = 3; REG Node = 'cnt\[15\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.531 ns" { clk~clkctrl cnt[15] } "NODE_NAME" } } { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 58.01 % ) " "Info: Total cell delay = 1.536 ns ( 58.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.112 ns ( 41.99 % ) " "Info: Total interconnect delay = 1.112 ns ( 41.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "2.648 ns" { clk clk~clkctrl cnt[15] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "2.648 ns" { clk {} clk~combout {} clk~clkctrl {} cnt[15] {} } { 0.000ns 0.000ns 0.118ns 0.994ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.877 ns + Longest register pin " "Info: + Longest register to pin delay is 3.877 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[15\] 1 REG LCFF_X7_Y27_N29 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X7_Y27_N29; Fanout = 3; REG Node = 'cnt\[15\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { cnt[15] } "NODE_NAME" } } { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.245 ns) + CELL(2.632 ns) 3.877 ns lcd_en 2 PIN PIN_K3 0 " "Info: 2: + IC(1.245 ns) + CELL(2.632 ns) = 3.877 ns; Loc. = PIN_K3; Fanout = 0; PIN Node = 'lcd_en'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "3.877 ns" { cnt[15] lcd_en } "NODE_NAME" } } { "src/lcd1602_driver.v" "" { Text "D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.632 ns ( 67.89 % ) " "Info: Total cell delay = 2.632 ns ( 67.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.245 ns ( 32.11 % ) " "Info: Total interconnect delay = 1.245 ns ( 32.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "3.877 ns" { cnt[15] lcd_en } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "3.877 ns" { cnt[15] {} lcd_en {} } { 0.000ns 1.245ns } { 0.000ns 2.632ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "2.648 ns" { clk clk~clkctrl cnt[15] } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "2.648 ns" { clk {} clk~combout {} clk~clkctrl {} cnt[15] {} } { 0.000ns 0.000ns 0.118ns 0.994ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "3.877 ns" { cnt[15] lcd_en } "NODE_NAME" } } { "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91/quartus/bin64/Technology_Viewer.qrui" "3.877 ns" { cnt[15] {} lcd_en {} } { 0.000ns 1.245ns } { 0.000ns 2.632ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II 64-Bit " "Info: Quartus II 64-Bit Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "215 " "Info: Peak virtual memory: 215 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 20 10:54:40 2012 " "Info: Processing ended: Sat Oct 20 10:54:40 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}