lcd1602_driver.sta.rpt

写给小白们的FPGA入门设计实验

TimeQuest Timing Analyzer report for lcd1602_driver
Sun Jul 03 16:00:46 2011
Quartus II Version 11.0 Build 157 04/27/2011 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. Clocks
  5. Slow Model Fmax Summary
  6. Slow Model Setup Summary
  7. Slow Model Hold Summary
  8. Slow Model Recovery Summary
  9. Slow Model Removal Summary
 10. Slow Model Minimum Pulse Width Summary
 11. Slow Model Setup: 'clk'
 12. Slow Model Hold: 'clk'
 13. Slow Model Minimum Pulse Width: 'clk'
 14. Clock to Output Times
 15. Minimum Clock to Output Times
 16. Fast Model Setup Summary
 17. Fast Model Hold Summary
 18. Fast Model Recovery Summary
 19. Fast Model Removal Summary
 20. Fast Model Minimum Pulse Width Summary
 21. Fast Model Setup: 'clk'
 22. Fast Model Hold: 'clk'
 23. Fast Model Minimum Pulse Width: 'clk'
 24. Clock to Output Times
 25. Minimum Clock to Output Times
 26. Multicorner Timing Analysis Summary
 27. Clock to Output Times
 28. Minimum Clock to Output Times
 29. Setup Transfers
 30. Hold Transfers
 31. Report TCCS
 32. Report RSKM
 33. Unconstrained Paths
 34. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                      ;
+--------------------+---------------------------------------------------+
; Quartus II Version ; Version 11.0 Build 157 04/27/2011 SJ Full Version ;
; Revision Name      ; lcd1602_driver                                    ;
; Device Family      ; Cyclone II                                        ;
; Device Name        ; EP2C35F672C6                                      ;
; Timing Models      ; Final                                             ;
; Delay Model        ; Combined                                          ;
; Rise/Fall Delays   ; Unavailable                                       ;
+--------------------+---------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.09        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ;   4.8%      ;
+----------------------------+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                          ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; clk        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk } ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+


+-------------------------------------------------+
; Slow Model Fmax Summary                         ;
+-----------+-----------------+------------+------+
; Fmax      ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------+------+
; 312.6 MHz ; 312.6 MHz       ; clk        ;      ;
+-----------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------+
; Slow Model Setup Summary       ;
+-------+--------+---------------+
; Clock ; Slack  ; End Point TNS ;
+-------+--------+---------------+
; clk   ; -2.199 ; -115.825      ;
+-------+--------+---------------+


+-------------------------------+
; Slow Model Hold Summary       ;
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
; clk   ; 0.391 ; 0.000         ;
+-------+-------+---------------+


-------------------------------
; Slow Model Recovery Summary ;
-------------------------------
No paths to report.