lcd1602_driver.map.rpt

来自「写给小白们的FPGA入门设计实验」· RPT 代码 · 共 308 行 · 第 1/5 页

; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ;   0.0%      ;
+----------------------------+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                            ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                        ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------+
; src/lcd1602_driver.v             ; yes             ; User Verilog HDL File  ; D:/Altera_Project/bingo_example/lcd1602_driver/src/lcd1602_driver.v ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 91    ;
;                                             ;       ;
; Total combinational functions               ; 53    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 28    ;
;     -- 3 input functions                    ; 7     ;
;     -- <=2 input functions                  ; 18    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 39    ;
;     -- arithmetic mode                      ; 14    ;
;                                             ;       ;
; Total registers                             ; 65    ;
;     -- Dedicated logic registers            ; 65    ;
;     -- I/O registers                        ; 0     ;