adder_4bits.v

写给小白们的FPGA入门设计实验

/*-------------------------------------------------------------------------
CONFIDENTIAL IN CONFIDENCE
This confidential and proprietary software may be only used as authorized
by a licensing agreement from CrazyBingo (Thereturnofbingo).
In the event of publication, the following notice is applicable:
Copyright (C) 2011-2012 CrazyBingo Corporation
The entire notice above must be reproduced on all authorized copies.
Author				:		CrazyBingo
Technology blogs 	: 		http://blog.chinaaet.com/crazybingo
							http://www.cnblogs.com/crazybingo
Eamil Address 		: 		[e-mail]
Filename			:		adder_4bits.v
Data				:		2012-10-20
Version				:		1.0
Description			:		This module is adder for 4 bits data.
Modification History	:
Data			By			Version			Change Description
===========================================================================
12/10/20		CrazyBingo	1.0				Original
--------------------------------------------------------------------------*/
`timescale 1 ns / 1 ns

module	adder_4bits
(
//	input	clk,
//	input	rst_n,
	
	input	[3:0]	x,
	input	[3:0]	y,
//	input			carry_in	//ahead module 
	
	output	[7:0]	sum
);

assign	sum = x + y;



endmodule