calculator_design.v

写给小白们的FPGA入门设计实验

/*-------------------------------------------------------------------------
CONFIDENTIAL IN CONFIDENCE
This confidential and proprietary software may be only used as authorized
by a licensing agreement from CrazyBingo (Thereturnofbingo).
In the event of publication, the following notice is applicable:
Copyright (C) 2011-2012 CrazyBingo Corporation
The entire notice above must be reproduced on all authorized copies.
Author				:		CrazyBingo
Technology blogs 	: 		http://blog.chinaaet.com/crazybingo
							http://www.cnblogs.com/crazybingo
Eamil Address 		: 		[e-mail]
Filename			:		Calculator_Design.v
Data				:		2012-11-01
Version				:		1.0
Description			:		Calculate for 2 data.
Modification History	:
Data			By			Version			Change Description
===========================================================================
12/11/01		CrazyBingo	1.0				Original
--------------------------------------------------------------------------*/
`timescale 1ns / 1ns
 
module	Calculator_Design
(
	input	clk,
	input	rst_n,

	input			key_xflag,	//trigger for data input
	input			key_yflag,	//trigger for data input
	input			key_sum,	//trigger for data input
	input			key_mult,	//trigger for data input
	
	input	[9:0]	key_switch,	//data 0-9
	
	output	[6:0]	oSEG3,
	output	[6:0]	oSEG2,
	output	[6:0]	oSEG1,
	output	[6:0]	oSEG0
);


//-----------------------------
reg	[3:0]	din;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		din <= 0;
	else
		case(key_switch)
		10'd1:		din <= 4'd0;
		10'd2:		din <= 4'd1;
		10'd4:		din <= 4'd2;
		10'd8:		din <= 4'd3;
		10'd16:		din <= 4'd4;
		10'd32:		din <= 4'd5;
		10'd64:		din <= 4'd6;
		10'd128:	din <= 4'd7;
		10'd256:	din <= 4'd8;
		10'd512:	din <= 4'd9;
		default:;
		endcase
end

//--------------------------------
wire		key_flag;
wire[3:0]	key_value;
key_scan
#(
	.KEY_WIDTH	(4)
)
u_key_scan
(
	.clk		(clk),
	.rst_n		(rst_n),	
	.key_data	({key_xflag, key_yflag, key_sum, key_mult}),	

	.key_flag	(key_flag),
	.key_value	(key_value)	
);

//------------------------
wire	[7:0]	sum_data;
adder_4bits	u_adder_4bits
(
	.x			(x),
	.y			(y),

	.sum		(sum_data)
);


//-------------------------
wire	[7:0]	mult_data;
mult_4bits	u_mult_4bits
(
	.x			(x),
	.y			(y),
	
	.mult_out	(mult_data)
);

//-------------------------------------
reg	[3:0]	x;
reg	[3:0]	y;
reg	[7:0]	result_data;
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		result_data <= 0;
	else if(key_flag)
		begin
		case(key_value)
		~4'b1000:	x <= din;
		~4'b0100:	y <= din;
		~4'b0010:	result_data <= sum_data;
		~4'b0001:	result_data <= mult_data;
//		4'b0111:	x <= din;
//		4'b1011:	y <= din;
//		4'b1101:	result_data <= sum_data;
//		4'b1110:	result_data <= mult_data;
		default:;
		endcase
		end
end


//-------------------------------
//hex2decimal convert
wire	[3:0]	shi_data = 	(result_data < 10)? 4'd0:
							(result_data < 20)?	4'd1:
							(result_data < 30)?	4'd2:
							(result_data < 40)? 4'd3:
							(result_data < 50)? 4'd4:
							(result_data < 60)? 4'd5:
							(result_data < 70)? 4'd6:
							(result_data < 80)? 4'd7:
							(result_data < 90)? 4'd8:	
							4'd9;

wire	[3:0]	ge_data = 	(result_data < 10)? result_data - 8'd0:
							(result_data < 20)?	result_data - 8'd10:
							(result_data < 30)?	result_data - 8'd20:
							(result_data < 40)? result_data - 8'd30:
							(result_data < 50)? result_data - 8'd40:
							(result_data < 60)? result_data - 8'd50:
							(result_data < 70)? result_data - 8'd60:
							(result_data < 80)? result_data - 8'd70:
							(result_data < 90)? result_data - 8'd80:	
							result_data - 8'd90;
							
//-------------------------					
Seg7_lut u_Seg7_lut3	
(	
	.iDIG	(x),
	.oSEG	(oSEG3)
);

//-------------------------	
Seg7_lut u_Seg7_lut2	
(	
	.iDIG	(y),
	.oSEG	(oSEG2)
);

//---------------------------
//display the result							
Seg7_lut u_Seg7_lut1	
(	
	.iDIG	(shi_data),
	.oSEG	(oSEG1)
);

//ge_data display
Seg7_lut u_Seg7_lut0
(	
	.iDIG	(ge_data),
	.oSEG	(oSEG0)
);

endmodule