📄 calculator_design.map.rpt
字号:
; 1 processor ; 100.0% ;
; 2 processors ; 0.0% ;
+----------------------------+-------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------+
; ../src/key_scan.v ; yes ; User Verilog HDL File ; D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v ;
; ../src/mult_4bits.v ; yes ; User Verilog HDL File ; D:/Altera_Project/LabTest/Calculator_Design/src/mult_4bits.v ;
; ../src/seg7_lut.v ; yes ; User Verilog HDL File ; D:/Altera_Project/LabTest/Calculator_Design/src/seg7_lut.v ;
; ../src/adder_4bits.v ; yes ; User Verilog HDL File ; D:/Altera_Project/LabTest/Calculator_Design/src/adder_4bits.v ;
; ../src/Calculator_Design.v ; yes ; User Verilog HDL File ; D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements ; 205 ;
; ; ;
; Total combinational functions ; 191 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 103 ;
; -- 3 input functions ; 37 ;
; -- <=2 input functions ; 51 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 156 ;
; -- arithmetic mode ; 35 ;
; ; ;
; Total registers ; 51 ;
; -- Dedicated logic registers ; 51 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 44 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 51 ;
; Total fan-out ; 832 ;
; Average fan-out ; 2.91 ;
+---------------------------------------------+-------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+--------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------+--------------+
; |Calculator_Design ; 191 (97) ; 51 (20) ; 0 ; 0 ; 0 ; 0 ; 44 ; 0 ; |Calculator_Design ; work ;
; |Seg7_lut:u_Seg7_lut0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Calculator_Design|Seg7_lut:u_Seg7_lut0 ; ;
; |Seg7_lut:u_Seg7_lut1| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Calculator_Design|Seg7_lut:u_Seg7_lut1 ; ;
; |Seg7_lut:u_Seg7_lut2| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Calculator_Design|Seg7_lut:u_Seg7_lut2 ; ;
; |Seg7_lut:u_Seg7_lut3| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Calculator_Design|Seg7_lut:u_Seg7_lut3 ; ;
; |adder_4bits:u_adder_4bits| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Calculator_Design|adder_4bits:u_adder_4bits ; ;
; |key_scan:u_key_scan| ; 36 (36) ; 31 (31) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Calculator_Design|key_scan:u_key_scan ; ;
; |mult_4bits:u_mult_4bits| ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Calculator_Design|mult_4bits:u_mult_4bits ; ;
+--------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 51 ;
; Number of registers using Synchronous Clear ; 20 ;
; Number of registers using Synchronous Load ; 5 ;
; Number of registers using Asynchronous Clear ; 43 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 19 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; key_scan:u_key_scan|key_data_r[0] ; 1 ;
; key_scan:u_key_scan|key_data_r[1] ; 1 ;
; key_scan:u_key_scan|key_data_r[3] ; 1 ;
; key_scan:u_key_scan|key_data_r[2] ; 1 ;
; Total number of inverted registers = 4 ; ;
+----------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; 16:1 ; 3 bits ; 30 LEs ; 3 LEs ; 27 LEs ; Yes ; |Calculator_Design|result_data[6] ;
; 16:1 ; 4 bits ; 40 LEs ; 4 LEs ; 36 LEs ; Yes ; |Calculator_Design|result_data[2] ;
; 7:1 ; 2 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |Calculator_Design|shi_data[2] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
+------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: key_scan:u_key_scan ;
+----------------+-------+-----------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-----------------------------------------+
; KEY_WIDTH ; 4 ; Signed Integer ;
+----------------+-------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version
Info: Processing started: Sat Nov 03 08:51:02 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Calculator_Design -c Calculator_Design
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Found 1 design units, including 1 entities, in source file /altera_project/labtest/calculator_design/src/key_scan.v
Info: Found entity 1: key_scan
Info: Found 1 design units, including 1 entities, in source file /altera_project/labtest/calculator_design/src/mult_4bits.v
Info: Found entity 1: mult_4bits
Info: Found 1 design units, including 1 entities, in source file /altera_project/labtest/calculator_design/src/seg7_lut.v
Info: Found entity 1: Seg7_lut
Info: Found 1 design units, including 1 entities, in source file /altera_project/labtest/calculator_design/src/adder_4bits.v
Info: Found entity 1: adder_4bits
Info: Found 1 design units, including 1 entities, in source file /altera_project/labtest/calculator_design/src/calculator_design.v
Info: Found entity 1: Calculator_Design
Info: Elaborating entity "Calculator_Design" for the top level hierarchy
Info (10264): Verilog HDL Case Statement information at Calculator_Design.v(49): all case item expressions in this case statement are onehot
Warning (10230): Verilog HDL assignment warning at Calculator_Design.v(140): truncated value with size 8 to match size of target (4)
Info: Elaborating entity "key_scan" for hierarchy "key_scan:u_key_scan"
Info: Elaborating entity "adder_4bits" for hierarchy "adder_4bits:u_adder_4bits"
Info: Elaborating entity "mult_4bits" for hierarchy "mult_4bits:u_mult_4bits"
Info: Elaborating entity "Seg7_lut" for hierarchy "Seg7_lut:u_Seg7_lut3"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 250 device resources after synthesis - the final resource count might be different
Info: Implemented 16 input pins
Info: Implemented 28 output pins
Info: Implemented 206 logic cells
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 266 megabytes
Info: Processing ended: Sat Nov 03 08:51:04 2012
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -