calculator_design.fit.qmsg

写给小白们的FPGA入门设计实验

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.351 ns register register " "Info: Estimated most critical path is register to register delay of 5.351 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_scan:u_key_scan\|key_cnt\[8\] 1 REG LAB_X60_Y20 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X60_Y20; Fanout = 3; REG Node = 'key_scan:u_key_scan\|key_cnt\[8\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { key_scan:u_key_scan|key_cnt[8] } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.949 ns) + CELL(0.150 ns) 1.099 ns key_scan:u_key_scan\|Equal2~2 2 COMB LAB_X60_Y19 1 " "Info: 2: + IC(0.949 ns) + CELL(0.150 ns) = 1.099 ns; Loc. = LAB_X60_Y19; Fanout = 1; COMB Node = 'key_scan:u_key_scan\|Equal2~2'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.099 ns" { key_scan:u_key_scan|key_cnt[8] key_scan:u_key_scan|Equal2~2 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.145 ns) + CELL(0.393 ns) 1.637 ns key_scan:u_key_scan\|Equal2~5 3 COMB LAB_X60_Y19 2 " "Info: 3: + IC(0.145 ns) + CELL(0.393 ns) = 1.637 ns; Loc. = LAB_X60_Y19; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|Equal2~5'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.538 ns" { key_scan:u_key_scan|Equal2~2 key_scan:u_key_scan|Equal2~5 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.150 ns) 2.202 ns key_scan:u_key_scan\|LessThan0~0 4 COMB LAB_X60_Y19 2 " "Info: 4: + IC(0.415 ns) + CELL(0.150 ns) = 2.202 ns; Loc. = LAB_X60_Y19; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|LessThan0~0'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.565 ns" { key_scan:u_key_scan|Equal2~5 key_scan:u_key_scan|LessThan0~0 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.873 ns) + CELL(0.414 ns) 3.489 ns key_scan:u_key_scan\|key_cnt\[0\]~21 5 COMB LAB_X60_Y20 2 " "Info: 5: + IC(0.873 ns) + CELL(0.414 ns) = 3.489 ns; Loc. = LAB_X60_Y20; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[0\]~21'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.287 ns" { key_scan:u_key_scan|LessThan0~0 key_scan:u_key_scan|key_cnt[0]~21 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.560 ns key_scan:u_key_scan\|key_cnt\[1\]~23 6 COMB LAB_X60_Y20 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 3.560 ns; Loc. = LAB_X60_Y20; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[1\]~23'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[0]~21 key_scan:u_key_scan|key_cnt[1]~23 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.631 ns key_scan:u_key_scan\|key_cnt\[2\]~25 7 COMB LAB_X60_Y20 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 3.631 ns; Loc. = LAB_X60_Y20; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[2\]~25'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[1]~23 key_scan:u_key_scan|key_cnt[2]~25 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.702 ns key_scan:u_key_scan\|key_cnt\[3\]~27 8 COMB LAB_X60_Y20 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 3.702 ns; Loc. = LAB_X60_Y20; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[3\]~27'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[2]~25 key_scan:u_key_scan|key_cnt[3]~27 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.773 ns key_scan:u_key_scan\|key_cnt\[4\]~29 9 COMB LAB_X60_Y20 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 3.773 ns; Loc. = LAB_X60_Y20; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[4\]~29'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[3]~27 key_scan:u_key_scan|key_cnt[4]~29 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.844 ns key_scan:u_key_scan\|key_cnt\[5\]~31 10 COMB LAB_X60_Y20 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 3.844 ns; Loc. = LAB_X60_Y20; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[5\]~31'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[4]~29 key_scan:u_key_scan|key_cnt[5]~31 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.915 ns key_scan:u_key_scan\|key_cnt\[6\]~33 11 COMB LAB_X60_Y20 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 3.915 ns; Loc. = LAB_X60_Y20; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[6\]~33'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[5]~31 key_scan:u_key_scan|key_cnt[6]~33 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.986 ns key_scan:u_key_scan\|key_cnt\[7\]~35 12 COMB LAB_X60_Y20 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 3.986 ns; Loc. = LAB_X60_Y20; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[7\]~35'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[6]~33 key_scan:u_key_scan|key_cnt[7]~35 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.057 ns key_scan:u_key_scan\|key_cnt\[8\]~37 13 COMB LAB_X60_Y20 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 4.057 ns; Loc. = LAB_X60_Y20; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[8\]~37'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[7]~35 key_scan:u_key_scan|key_cnt[8]~37 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.128 ns key_scan:u_key_scan\|key_cnt\[9\]~39 14 COMB LAB_X60_Y20 2 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 4.128 ns; Loc. = LAB_X60_Y20; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[9\]~39'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[8]~37 key_scan:u_key_scan|key_cnt[9]~39 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.090 ns) + CELL(0.071 ns) 4.289 ns key_scan:u_key_scan\|key_cnt\[10\]~41 15 COMB LAB_X60_Y19 2 " "Info: 15: + IC(0.090 ns) + CELL(0.071 ns) = 4.289 ns; Loc. = LAB_X60_Y19; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[10\]~41'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.161 ns" { key_scan:u_key_scan|key_cnt[9]~39 key_scan:u_key_scan|key_cnt[10]~41 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.360 ns key_scan:u_key_scan\|key_cnt\[11\]~43 16 COMB LAB_X60_Y19 2 " "Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 4.360 ns; Loc. = LAB_X60_Y19; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[11\]~43'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[10]~41 key_scan:u_key_scan|key_cnt[11]~43 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.431 ns key_scan:u_key_scan\|key_cnt\[12\]~45 17 COMB LAB_X60_Y19 2 " "Info: 17: + IC(0.000 ns) + CELL(0.071 ns) = 4.431 ns; Loc. = LAB_X60_Y19; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[12\]~45'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[11]~43 key_scan:u_key_scan|key_cnt[12]~45 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.502 ns key_scan:u_key_scan\|key_cnt\[13\]~47 18 COMB LAB_X60_Y19 2 " "Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 4.502 ns; Loc. = LAB_X60_Y19; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[13\]~47'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[12]~45 key_scan:u_key_scan|key_cnt[13]~47 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.573 ns key_scan:u_key_scan\|key_cnt\[14\]~49 19 COMB LAB_X60_Y19 2 " "Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 4.573 ns; Loc. = LAB_X60_Y19; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[14\]~49'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[13]~47 key_scan:u_key_scan|key_cnt[14]~49 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.644 ns key_scan:u_key_scan\|key_cnt\[15\]~51 20 COMB LAB_X60_Y19 2 " "Info: 20: + IC(0.000 ns) + CELL(0.071 ns) = 4.644 ns; Loc. = LAB_X60_Y19; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[15\]~51'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[14]~49 key_scan:u_key_scan|key_cnt[15]~51 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.715 ns key_scan:u_key_scan\|key_cnt\[16\]~53 21 COMB LAB_X60_Y19 2 " "Info: 21: + IC(0.000 ns) + CELL(0.071 ns) = 4.715 ns; Loc. = LAB_X60_Y19; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[16\]~53'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[15]~51 key_scan:u_key_scan|key_cnt[16]~53 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.786 ns key_scan:u_key_scan\|key_cnt\[17\]~55 22 COMB LAB_X60_Y19 2 " "Info: 22: + IC(0.000 ns) + CELL(0.071 ns) = 4.786 ns; Loc. = LAB_X60_Y19; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[17\]~55'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[16]~53 key_scan:u_key_scan|key_cnt[17]~55 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.857 ns key_scan:u_key_scan\|key_cnt\[18\]~57 23 COMB LAB_X60_Y19 1 " "Info: 23: + IC(0.000 ns) + CELL(0.071 ns) = 4.857 ns; Loc. = LAB_X60_Y19; Fanout = 1; COMB Node = 'key_scan:u_key_scan\|key_cnt\[18\]~57'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[17]~55 key_scan:u_key_scan|key_cnt[18]~57 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 5.267 ns key_scan:u_key_scan\|key_cnt\[19\]~58 24 COMB LAB_X60_Y19 1 " "Info: 24: + IC(0.000 ns) + CELL(0.410 ns) = 5.267 ns; Loc. = LAB_X60_Y19; Fanout = 1; COMB Node = 'key_scan:u_key_scan\|key_cnt\[19\]~58'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.410 ns" { key_scan:u_key_scan|key_cnt[18]~57 key_scan:u_key_scan|key_cnt[19]~58 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 5.351 ns key_scan:u_key_scan\|key_cnt\[19\] 25 REG LAB_X60_Y19 2 " "Info: 25: + IC(0.000 ns) + CELL(0.084 ns) = 5.351 ns; Loc. = LAB_X60_Y19; Fanout = 2; REG Node = 'key_scan:u_key_scan\|key_cnt\[19\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.084 ns" { key_scan:u_key_scan|key_cnt[19]~58 key_scan:u_key_scan|key_cnt[19] } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.879 ns ( 53.80 % ) " "Info: Total cell delay = 2.879 ns ( 53.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.472 ns ( 46.20 % ) " "Info: Total interconnect delay = 2.472 ns ( 46.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "5.351 ns" { key_scan:u_key_scan|key_cnt[8] key_scan:u_key_scan|Equal2~2 key_scan:u_key_scan|Equal2~5 key_scan:u_key_scan|LessThan0~0 key_scan:u_key_scan|key_cnt[0]~21 key_scan:u_key_scan|key_cnt[1]~23 key_scan:u_key_scan|key_cnt[2]~25 key_scan:u_key_scan|key_cnt[3]~27 key_scan:u_key_scan|key_cnt[4]~29 key_scan:u_key_scan|key_cnt[5]~31 key_scan:u_key_scan|key_cnt[6]~33 key_scan:u_key_scan|key_cnt[7]~35 key_scan:u_key_scan|key_cnt[8]~37 key_scan:u_key_scan|key_cnt[9]~39 key_scan:u_key_scan|key_cnt[10]~41 key_scan:u_key_scan|key_cnt[11]~43 key_scan:u_key_scan|key_cnt[12]~45 key_scan:u_key_scan|key_cnt[13]~47 key_scan:u_key_scan|key_cnt[14]~49 key_scan:u_key_scan|key_cnt[15]~51 key_scan:u_key_scan|key_cnt[16]~53 key_scan:u_key_scan|key_cnt[17]~55 key_scan:u_key_scan|key_cnt[18]~57 key_scan:u_key_scan|key_cnt[19]~58 key_scan:u_key_scan|key_cnt[19] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X55_Y12 X65_Y23 " "Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X55_Y12 to location X65_Y23" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "28 " "Warning: Found 28 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG3\[0\] 0 " "Info: Pin \"oSEG3\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG3\[1\] 0 " "Info: Pin \"oSEG3\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG3\[2\] 0 " "Info: Pin \"oSEG3\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG3\[3\] 0 " "Info: Pin \"oSEG3\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG3\[4\] 0 " "Info: Pin \"oSEG3\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG3\[5\] 0 " "Info: Pin \"oSEG3\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG3\[6\] 0 " "Info: Pin \"oSEG3\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG2\[0\] 0 " "Info: Pin \"oSEG2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG2\[1\] 0 " "Info: Pin \"oSEG2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG2\[2\] 0 " "Info: Pin \"oSEG2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG2\[3\] 0 " "Info: Pin \"oSEG2\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG2\[4\] 0 " "Info: Pin \"oSEG2\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG2\[5\] 0 " "Info: Pin \"oSEG2\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG2\[6\] 0 " "Info: Pin \"oSEG2\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG1\[0\] 0 " "Info: Pin \"oSEG1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG1\[1\] 0 " "Info: Pin \"oSEG1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG1\[2\] 0 " "Info: Pin \"oSEG1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG1\[3\] 0 " "Info: Pin \"oSEG1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG1\[4\] 0 " "Info: Pin \"oSEG1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG1\[5\] 0 " "Info: Pin \"oSEG1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG1\[6\] 0 " "Info: Pin \"oSEG1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG0\[0\] 0 " "Info: Pin \"oSEG0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG0\[1\] 0 " "Info: Pin \"oSEG0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG0\[2\] 0 " "Info: Pin \"oSEG0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG0\[3\] 0 " "Info: Pin \"oSEG0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG0\[4\] 0 " "Info: Pin \"oSEG0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG0\[5\] 0 " "Info: Pin \"oSEG0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oSEG0\[6\] 0 " "Info: Pin \"oSEG0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/Altera_Project/LabTest/Calculator_Design/dev/Calculator_Design.fit.smsg " "Info: Generated suppressed messages file D:/Altera_Project/LabTest/Calculator_Design/dev/Calculator_Design.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II 64-Bit " "Info: Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "351 " "Info: Peak virtual memory: 351 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 03 08:51:09 2012 " "Info: Processing ended: Sat Nov 03 08:51:09 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Info: Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}