prev_cmp_calculator_design.qmsg

写给小白们的FPGA入门设计实验

{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/Altera_Project/LabTest/Calculator_Design/dev/Calculator_Design.fit.smsg " "Info: Generated suppressed messages file D:/Altera_Project/LabTest/Calculator_Design/dev/Calculator_Design.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II 64-Bit " "Info: Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "351 " "Info: Peak virtual memory: 351 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 02 13:34:42 2012 " "Info: Processing ended: Fri Nov 02 13:34:42 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Info: Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Info: Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version " "Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 02 13:34:43 2012 " "Info: Processing started: Fri Nov 02 13:34:43 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Calculator_Design -c Calculator_Design " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Calculator_Design -c Calculator_Design" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "304 " "Info: Peak virtual memory: 304 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 02 13:34:45 2012 " "Info: Processing ended: Fri Nov 02 13:34:45 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II 64-Bit " "Info: Running Quartus II 64-Bit Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version " "Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 02 13:34:46 2012 " "Info: Processing started: Fri Nov 02 13:34:46 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Calculator_Design -c Calculator_Design --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Calculator_Design -c Calculator_Design --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 25 -1 0 } } { "c:/altera/91/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/91/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register key_scan:u_key_scan\|key_cnt\[3\] register key_scan:u_key_scan\|key_cnt\[19\] 178.25 MHz 5.61 ns Internal " "Info: Clock \"clk\" has Internal fmax of 178.25 MHz between source register \"key_scan:u_key_scan\|key_cnt\[3\]\" and destination register \"key_scan:u_key_scan\|key_cnt\[19\]\" (period= 5.61 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.398 ns + Longest register register " "Info: + Longest register to register delay is 5.398 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_scan:u_key_scan\|key_cnt\[3\] 1 REG LCFF_X60_Y20_N19 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X60_Y20_N19; Fanout = 3; REG Node = 'key_scan:u_key_scan\|key_cnt\[3\]'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "" { key_scan:u_key_scan|key_cnt[3] } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.791 ns) + CELL(0.393 ns) 1.184 ns key_scan:u_key_scan\|Equal2~1 2 COMB LCCOMB_X60_Y19_N20 1 " "Info: 2: + IC(0.791 ns) + CELL(0.393 ns) = 1.184 ns; Loc. = LCCOMB_X60_Y19_N20; Fanout = 1; COMB Node = 'key_scan:u_key_scan\|Equal2~1'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.184 ns" { key_scan:u_key_scan|key_cnt[3] key_scan:u_key_scan|Equal2~1 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.268 ns) + CELL(0.410 ns) 1.862 ns key_scan:u_key_scan\|Equal2~5 3 COMB LCCOMB_X60_Y19_N28 2 " "Info: 3: + IC(0.268 ns) + CELL(0.410 ns) = 1.862 ns; Loc. = LCCOMB_X60_Y19_N28; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|Equal2~5'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.678 ns" { key_scan:u_key_scan|Equal2~1 key_scan:u_key_scan|Equal2~5 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.150 ns) 2.266 ns key_scan:u_key_scan\|LessThan0~0 4 COMB LCCOMB_X60_Y19_N22 2 " "Info: 4: + IC(0.254 ns) + CELL(0.150 ns) = 2.266 ns; Loc. = LCCOMB_X60_Y19_N22; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|LessThan0~0'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.404 ns" { key_scan:u_key_scan|Equal2~5 key_scan:u_key_scan|LessThan0~0 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.716 ns) + CELL(0.393 ns) 3.375 ns key_scan:u_key_scan\|key_cnt\[0\]~21 5 COMB LCCOMB_X60_Y20_N12 2 " "Info: 5: + IC(0.716 ns) + CELL(0.393 ns) = 3.375 ns; Loc. = LCCOMB_X60_Y20_N12; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[0\]~21'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "1.109 ns" { key_scan:u_key_scan|LessThan0~0 key_scan:u_key_scan|key_cnt[0]~21 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 3.534 ns key_scan:u_key_scan\|key_cnt\[1\]~23 6 COMB LCCOMB_X60_Y20_N14 2 " "Info: 6: + IC(0.000 ns) + CELL(0.159 ns) = 3.534 ns; Loc. = LCCOMB_X60_Y20_N14; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[1\]~23'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.159 ns" { key_scan:u_key_scan|key_cnt[0]~21 key_scan:u_key_scan|key_cnt[1]~23 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.605 ns key_scan:u_key_scan\|key_cnt\[2\]~25 7 COMB LCCOMB_X60_Y20_N16 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 3.605 ns; Loc. = LCCOMB_X60_Y20_N16; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[2\]~25'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[1]~23 key_scan:u_key_scan|key_cnt[2]~25 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.676 ns key_scan:u_key_scan\|key_cnt\[3\]~27 8 COMB LCCOMB_X60_Y20_N18 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 3.676 ns; Loc. = LCCOMB_X60_Y20_N18; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[3\]~27'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[2]~25 key_scan:u_key_scan|key_cnt[3]~27 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.747 ns key_scan:u_key_scan\|key_cnt\[4\]~29 9 COMB LCCOMB_X60_Y20_N20 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 3.747 ns; Loc. = LCCOMB_X60_Y20_N20; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[4\]~29'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[3]~27 key_scan:u_key_scan|key_cnt[4]~29 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.818 ns key_scan:u_key_scan\|key_cnt\[5\]~31 10 COMB LCCOMB_X60_Y20_N22 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 3.818 ns; Loc. = LCCOMB_X60_Y20_N22; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[5\]~31'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[4]~29 key_scan:u_key_scan|key_cnt[5]~31 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.889 ns key_scan:u_key_scan\|key_cnt\[6\]~33 11 COMB LCCOMB_X60_Y20_N24 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 3.889 ns; Loc. = LCCOMB_X60_Y20_N24; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[6\]~33'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[5]~31 key_scan:u_key_scan|key_cnt[6]~33 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.960 ns key_scan:u_key_scan\|key_cnt\[7\]~35 12 COMB LCCOMB_X60_Y20_N26 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 3.960 ns; Loc. = LCCOMB_X60_Y20_N26; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[7\]~35'" {  } { { "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91/quartus/bin64/TimingClosureFloorplan.fld" "" "0.071 ns" { key_scan:u_key_scan|key_cnt[6]~33 key_scan:u_key_scan|key_cnt[7]~35 } "NODE_NAME" } } { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.031 ns key_scan:u_key_scan\|key_cnt\[8\]~37 13 COMB LCCOMB_X60_Y20_N28 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 4.031 ns; Loc. = LCCOMB_X60_Y20_N28; Fanout = 2; COMB Node = 'key_scan:u_key_scan\|key_cnt\[8\]~37'" {  } { { "c:/altera/91/quartus/b