prev_cmp_calculator_design.qmsg

写给小白们的FPGA入门设计实验

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Info: Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version " "Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 02 13:34:35 2012 " "Info: Processing started: Fri Nov 02 13:34:35 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Calculator_Design -c Calculator_Design " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Calculator_Design -c Calculator_Design" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/altera_project/labtest/calculator_design/src/key_scan.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file /altera_project/labtest/calculator_design/src/key_scan.v" { { "Info" "ISGN_ENTITY_NAME" "1 key_scan " "Info: Found entity 1: key_scan" {  } { { "../src/key_scan.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/key_scan.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/altera_project/labtest/calculator_design/src/mult_4bits.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file /altera_project/labtest/calculator_design/src/mult_4bits.v" { { "Info" "ISGN_ENTITY_NAME" "1 mult_4bits " "Info: Found entity 1: mult_4bits" {  } { { "../src/mult_4bits.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/mult_4bits.v" 22 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/altera_project/labtest/calculator_design/src/seg7_lut.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file /altera_project/labtest/calculator_design/src/seg7_lut.v" { { "Info" "ISGN_ENTITY_NAME" "1 Seg7_lut " "Info: Found entity 1: Seg7_lut" {  } { { "../src/seg7_lut.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/seg7_lut.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/altera_project/labtest/calculator_design/src/adder_4bits.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file /altera_project/labtest/calculator_design/src/adder_4bits.v" { { "Info" "ISGN_ENTITY_NAME" "1 adder_4bits " "Info: Found entity 1: adder_4bits" {  } { { "../src/adder_4bits.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/adder_4bits.v" 23 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/altera_project/labtest/calculator_design/src/calculator_design.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file /altera_project/labtest/calculator_design/src/calculator_design.v" { { "Info" "ISGN_ENTITY_NAME" "1 Calculator_Design " "Info: Found entity 1: Calculator_Design" {  } { { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 23 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSGN_FILE_IS_MISSING" "../src/data_processor.v " "Warning: Can't analyze file -- file ../src/data_processor.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "Calculator_Design " "Info: Elaborating entity \"Calculator_Design\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "Calculator_Design.v(49) " "Info (10264): Verilog HDL Case Statement information at Calculator_Design.v(49): all case item expressions in this case statement are onehot" {  } { { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 49 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 Calculator_Design.v(140) " "Warning (10230): Verilog HDL assignment warning at Calculator_Design.v(140): truncated value with size 8 to match size of target (4)" {  } { { "../src/Calculator_Design.v" "" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 140 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "key_scan key_scan:u_key_scan " "Info: Elaborating entity \"key_scan\" for hierarchy \"key_scan:u_key_scan\"" {  } { { "../src/Calculator_Design.v" "u_key_scan" { Text "D:/Altera_Project/LabTest/Calculator_Design/src/Calculator_Design.v" 79 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}