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📄 calculator_design.pin

📁 写给小白们的FPGA入门设计实验
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 -- Copyright (C) 1991-2010 Altera Corporation
 -- Your use of Altera Corporation's design tools, logic functions 
 -- and other software and tools, and its AMPP partner logic 
 -- functions, and any output files from any of the foregoing 
 -- (including device programming or simulation files), and any 
 -- associated documentation or information are expressly subject 
 -- to the terms and conditions of the Altera Program License 
 -- Subscription Agreement, Altera MegaCore Function License 
 -- Agreement, or other applicable license agreement, including, 
 -- without limitation, that your use is for the sole purpose of 
 -- programming logic devices manufactured by Altera and sold by 
 -- Altera or its authorized distributors.  Please refer to the 
 -- applicable agreement for further details.
 -- 
 -- This is a Quartus II output file. It is for reporting purposes only, and is
 -- not intended for use as a Quartus II input file. This file cannot be used
 -- to make Quartus II pin assignments - for instructions on how to make pin
 -- assignments, please see Quartus II help.
 ---------------------------------------------------------------------------------



 ---------------------------------------------------------------------------------
 -- NC            : No Connect. This pin has no internal connection to the device.
 -- DNU           : Do Not Use. This pin MUST NOT be connected.
 -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
 -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
 --                 of its bank.
 --					Bank 1:		3.3V
 --					Bank 2:		3.3V
 --					Bank 3:		3.3V
 --					Bank 4:		3.3V
 --					Bank 5:		3.3V
 --					Bank 6:		3.3V
 --					Bank 7:		3.3V
 --					Bank 8:		3.3V
 -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
 --					It can also be used to report unused dedicated pins. The connection
 --					on the board for unused dedicated pins depends on whether this will
 --					be used in a future design. One example is device migration. When
 --					using device migration, refer to the device pin-tables. If it is a
 --					GND pin in the pin table or if it will not be used in a future design
 --					for another purpose the it MUST be connected to GND. If it is an unused
 --					dedicated pin, then it can be connected to a valid signal on the board
 --					(low, high, or toggling) if that signal is required for a different
 --					revision of the design.
 -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
 --					This pin should be connected to GND. It may also be connected  to a
 --					valid signal  on the board  (low, high, or toggling)  if that signal
 --					is required for a different revision of the design.
 -- GND*          : Unused  I/O  pin.   For transceiver I/O banks, connect each pin marked GND*
 --           	    either individually through a 10k Ohm resistor to GND or tie all pins
 --           	    together and connect through a single 10k Ohm resistor to GND.
 --           	    For non-transceiver I/O banks, connect each pin marked GND* directly to GND
 --           	    or leave it unconnected.
 -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
 -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
 -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
 -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
 -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
 ---------------------------------------------------------------------------------



 ---------------------------------------------------------------------------------
 -- Pin directions (input, output or bidir) are based on device operating in user mode.
 ---------------------------------------------------------------------------------

Quartus II 64-Bit Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version
CHIP  "Calculator_Design"  ASSIGNED TO AN: EP2C35F672C6

Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
-------------------------------------------------------------------------------------------------------------
GND                          : A2        : gnd    :                   :         :           :                
VCCIO3                       : A3        : power  :                   : 3.3V    : 3         :                
RESERVED_INPUT               : A4        :        :                   :         : 3         :                
RESERVED_INPUT               : A5        :        :                   :         : 3         :                
RESERVED_INPUT               : A6        :        :                   :         : 3         :                
RESERVED_INPUT               : A7        :        :                   :         : 3         :                
RESERVED_INPUT               : A8        :        :                   :         : 3         :                
RESERVED_INPUT               : A9        :        :                   :         : 3         :                
RESERVED_INPUT               : A10       :        :                   :         : 3         :                
VCCIO3                       : A11       : power  :                   : 3.3V    : 3         :                
GND                          : A12       : gnd    :                   :         :           :                
key_switch[9]                : A13       : input  : 3.3-V LVTTL       :         : 4         : Y              
RESERVED_INPUT               : A14       :        :                   :         : 4         :                
GND                          : A15       : gnd    :                   :         :           :                
VCCIO4                       : A16       : power  :                   : 3.3V    : 4         :                
RESERVED_INPUT               : A17       :        :                   :         : 4         :                
RESERVED_INPUT               : A18       :        :                   :         : 4         :                
RESERVED_INPUT               : A19       :        :                   :         : 4         :                
RESERVED_INPUT               : A20       :        :                   :         : 4         :                
RESERVED_INPUT               : A21       :        :                   :         : 4         :                
RESERVED_INPUT               : A22       :        :                   :         : 4         :                
RESERVED_INPUT               : A23       :        :                   :         : 4         :                
VCCIO4                       : A24       : power  :                   : 3.3V    : 4         :                
GND                          : A25       : gnd    :                   :         :           :                
RESERVED_INPUT               : AA1       :        :                   :         : 1         :                
RESERVED_INPUT               : AA2       :        :                   :         : 1         :                
RESERVED_INPUT               : AA3       :        :                   :         : 1         :                
RESERVED_INPUT               : AA4       :        :                   :         : 1         :                
RESERVED_INPUT               : AA5       :        :                   :         : 1         :                
RESERVED_INPUT               : AA6       :        :                   :         : 1         :                
RESERVED_INPUT               : AA7       :        :                   :         : 1         :                
VCCA_PLL1                    : AA8       : power  :                   : 1.2V    :           :                
RESERVED_INPUT               : AA9       :        :                   :         : 8         :                
RESERVED_INPUT               : AA10      :        :                   :         : 8         :                
RESERVED_INPUT               : AA11      :        :                   :         : 8         :                
RESERVED_INPUT               : AA12      :        :                   :         : 8         :                
RESERVED_INPUT               : AA13      :        :                   :         : 7         :                
RESERVED_INPUT               : AA14      :        :                   :         : 7         :                
RESERVED_INPUT               : AA15      :        :                   :         : 7         :                
RESERVED_INPUT               : AA16      :        :                   :         : 7         :                
RESERVED_INPUT               : AA17      :        :                   :         : 7         :                
RESERVED_INPUT               : AA18      :        :                   :         : 7         :                
VCCA_PLL4                    : AA19      : power  :                   : 1.2V    :           :                
RESERVED_INPUT               : AA20      :        :                   :         : 7         :                
GND_PLL4                     : AA21      : gnd    :                   :         :           :                
VCCIO6                       : AA22      : power  :                   : 3.3V    : 6         :                
oSEG1[5]                     : AA23      : output : 3.3-V LVTTL       :         : 6         : Y              
oSEG1[4]                     : AA24      : output : 3.3-V LVTTL       :         : 6         : Y              
oSEG3[1]                     : AA25      : output : 3.3-V LVTTL       :         : 6         : Y              
oSEG3[2]                     : AA26      : output : 3.3-V LVTTL       :         : 6         : Y              
RESERVED_INPUT               : AB1       :        :                   :         : 1         :                
RESERVED_INPUT               : AB2       :        :                   :         : 1         :                

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