flip.vhd

来自「4位二进制密码锁,可能会对别人有点帮助,大家下来看看把」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity flip is
port(clk : in std_logic;--计时时钟
     clr : in std_logic;--复位
     h:in std_logic_vector(5 downto 0);
     m: out std_logic_vector(5 downto 0));
end ;
architecture behave of flip is
signal m0: std_logic_vector(5 downto 0) := "000111";
begin
process(clk,clr)
begin
if clr ='1' then m0 <= "000111";
elsif clk'event and clk = '1' then
m0 (5 downto 0) <= h(5 downto 0);
end if;
end process;
m (5 downto 0) <= m0(5 downto 0);
end behave;