clock.map.qmsg

4位二进制密码锁,可能会对别人有点帮助,大家下来看看把

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 16 20:22:20 2008 " "Info: Processing started: Tue Dec 16 20:22:20 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "compare.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file compare.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 compare-behave " "Info: Found design unit 1: compare-behave" {  } { { "compare.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/compare.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 compare " "Info: Found entity 1: compare" {  } { { "compare.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/compare.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "flip.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file flip.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 flip-behave " "Info: Found design unit 1: flip-behave" {  } { { "flip.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/flip.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 flip " "Info: Found entity 1: flip" {  } { { "flip.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/flip.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "input.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file input.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 input-behave " "Info: Found design unit 1: input-behave" {  } { { "input.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/input.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 input " "Info: Found entity 1: input" {  } { { "input.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/input.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "output.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file output.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 output-behave " "Info: Found design unit 1: output-behave" {  } { { "output.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/output.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 output " "Info: Found entity 1: output" {  } { { "output.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/output.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock-behave " "Info: Found design unit 1: clock-behave" {  } { { "clock.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/clock.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/clock.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "input input:u1 " "Info: Elaborating entity \"input\" for hierarchy \"input:u1\"" {  } { { "clock.vhd" "u1" { Text "C:/Documents and Settings/user/桌面/suo/clock.vhd" 37 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "m0 input.vhd(14) " "Warning (10631): VHDL Process Statement warning at input.vhd(14): inferring latch(es) for signal or variable \"m0\", which holds its previous value in one or more paths through the process" {  } { { "input.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/input.vhd" 14 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "n0 input.vhd(29) " "Warning (10631): VHDL Process Statement warning at input.vhd(29): inferring latch(es) for signal or variable \"n0\", which holds its previous value in one or more paths through the process" {  } { { "input.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/input.vhd" 29 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "n0\[0\] input.vhd(29) " "Info (10041): Verilog HDL or VHDL info at input.vhd(29): inferred latch for \"n0\[0\]\"" {  } { { "input.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/input.vhd" 29 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "n0\[1\] input.vhd(29) " "Info (10041): Verilog HDL or VHDL info at input.vhd(29): inferred latch for \"n0\[1\]\"" {  } { { "input.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/input.vhd" 29 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "n0\[2\] input.vhd(29) " "Info (10041): Verilog HDL or VHDL info at input.vhd(29): inferred latch for \"n0\[2\]\"" {  } { { "input.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/input.vhd" 29 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "m0\[0\] input.vhd(14) " "Info (10041): Verilog HDL or VHDL info at input.vhd(14): inferred latch for \"m0\[0\]\"" {  } { { "input.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/input.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "m0\[1\] input.vhd(14) " "Info (10041): Verilog HDL or VHDL info at input.vhd(14): inferred latch for \"m0\[1\]\"" {  } { { "input.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/input.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "m0\[2\] input.vhd(14) " "Info (10041): Verilog HDL or VHDL info at input.vhd(14): inferred latch for \"m0\[2\]\"" {  } { { "input.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/input.vhd" 14 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "compare compare:u2 " "Info: Elaborating entity \"compare\" for hierarchy \"compare:u2\"" {  } { { "clock.vhd" "u2" { Text "C:/Documents and Settings/user/桌面/suo/clock.vhd" 38 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ok compare.vhd(26) " "Warning (10492): VHDL Process Statement warning at compare.vhd(26): signal \"ok\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "compare.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/compare.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "f0 compare.vhd(15) " "Warning (10631): VHDL Process Statement warning at compare.vhd(15): inferring latch(es) for signal or variable \"f0\", which holds its previous value in one or more paths through the process" {  } { { "compare.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/compare.vhd" 15 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "f0\[0\] compare.vhd(15) " "Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for \"f0\[0\]\"" {  } { { "compare.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/compare.vhd" 15 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "f0\[1\] compare.vhd(15) " "Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for \"f0\[1\]\"" {  } { { "compare.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/compare.vhd" 15 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "f0\[2\] compare.vhd(15) " "Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for \"f0\[2\]\"" {  } { { "compare.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/compare.vhd" 15 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "f0\[3\] compare.vhd(15) " "Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for \"f0\[3\]\"" {  } { { "compare.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/compare.vhd" 15 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "f0\[4\] compare.vhd(15) " "Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for \"f0\[4\]\"" {  } { { "compare.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/compare.vhd" 15 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "f0\[5\] compare.vhd(15) " "Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for \"f0\[5\]\"" {  } { { "compare.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/compare.vhd" 15 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "flip flip:u3 " "Info: Elaborating entity \"flip\" for hierarchy \"flip:u3\"" {  } { { "clock.vhd" "u3" { Text "C:/Documents and Settings/user/桌面/suo/clock.vhd" 39 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "output output:u4 " "Info: Elaborating entity \"output\" for hierarchy \"output:u4\"" {  } { { "clock.vhd" "u4" { Text "C:/Documents and Settings/user/桌面/suo/clock.vhd" 40 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "flip.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/flip.vhd" 15 -1 0 } } { "flip.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/flip.vhd" 15 -1 0 } } { "flip.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/flip.vhd" 15 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "41 " "Info: Implemented 41 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "22 " "Info: Implemented 22 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 16 20:22:21 2008 " "Info: Processing ended: Tue Dec 16 20:22:21 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}