📄 input.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity input is
port(en: in std_logic; --进入开锁键?
a,b: in std_logic_vector(2 downto 0);--A代表密码的个位,B代表密码的十位
m1,n1: out std_logic_vector(2 downto 0);--密码个位十位的输出
c: out std_logic_vector(5 downto 0));--高三位存密码的十位,低三位存密码的个位
end;
architecture behave of input is
signal m0,n0: std_logic_vector(2 downto 0);
signal c0: std_logic_vector(5 downto 0);
begin
process(en,a,m0)
begin
if en ='0' then m0 <= "000";
elsif a = "000" then m0 <= "000";
elsif a = "001" then m0 <= "001";
elsif a = "010" then m0 <= "010";
elsif a = "011" then m0 <= "011";
elsif a = "100" then m0 <= "100";
elsif a = "101" then m0 <= "101";
elsif a = "110" then m0 <= "110";
elsif a = "111" then m0 <= "111";
--elsif a = "1001" then m0 <= "1000";
--elsif a = "1010" then m0 <= "1001";
end if;
end process;
process(en,b,n0)
begin
if en ='0' then n0 <= "000";
elsif b = "000" then n0 <= "000";
elsif b = "001" then n0 <= "001";
elsif b = "010" then n0 <= "010";
elsif b = "011" then n0 <= "011";
elsif b = "100" then n0 <= "100";
elsif b = "101" then n0 <= "101";
elsif b = "110" then n0 <= "110";
elsif b = "111" then n0 <= "111";
--elsif b = "1001" then n0 <= "1000";
--elsif b = "1010" then n0 <= "1001";
end if;
end process;
c(2 downto 0) <= a( 2 downto 0);
c(5 downto 3) <= b( 2 downto 0);
m1(2 downto 0) <= m0( 2 downto 0);
n1(2 downto 0) <= n0( 2 downto 0);
end behave;
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