output.vhd

4位二进制密码锁,可能会对别人有点帮助,大家下来看看把

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity output is
port (n: in std_logic;     --输入密码结果的输出
      o,p,q: out std_logic);
end;
architecture behave of output is
signal o0,p0,q0 : std_logic := '0';
begin
process(n)
begin
if n = '1' then
o0 <= '1';--绿灯
p0 <= '0';--红灯
q0 <= '0';
else
o0 <= '0';
p0 <= '1';
q0 <= '1';--报警器
end if;
end process;
o <= o0;
p <= p0;
q <= q0;
end behave;