mchange100.tan.rpt

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

; N/A           ; None        ; -3.059 ns ; m[1] ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; -5.263 ns ; m[6] ; q[6]~reg0 ; clk      ;
; N/A           ; None        ; -5.669 ns ; m[4] ; q[4]~reg0 ; clk      ;
; N/A           ; None        ; -5.703 ns ; m[5] ; q[5]~reg0 ; clk      ;
; N/A           ; None        ; -6.035 ns ; m[3] ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; -6.101 ns ; m[0] ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; -6.185 ns ; m[5] ; q[6]~reg0 ; clk      ;
; N/A           ; None        ; -6.189 ns ; m[3] ; q[4]~reg0 ; clk      ;
; N/A           ; None        ; -6.284 ns ; m[4] ; q[5]~reg0 ; clk      ;
; N/A           ; None        ; -6.340 ns ; m[4] ; q[6]~reg0 ; clk      ;
; N/A           ; None        ; -6.406 ns ; m[3] ; q[5]~reg0 ; clk      ;
; N/A           ; None        ; -6.462 ns ; m[3] ; q[6]~reg0 ; clk      ;
; N/A           ; None        ; -6.667 ns ; m[0] ; q[2]~reg0 ; clk      ;
; N/A           ; None        ; -6.825 ns ; m[0] ; q[4]~reg0 ; clk      ;
; N/A           ; None        ; -7.014 ns ; m[6] ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; -7.014 ns ; m[6] ; q[5]~reg0 ; clk      ;
; N/A           ; None        ; -7.014 ns ; m[6] ; q[2]~reg0 ; clk      ;
; N/A           ; None        ; -7.014 ns ; m[6] ; q[4]~reg0 ; clk      ;
; N/A           ; None        ; -7.014 ns ; m[6] ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; -7.014 ns ; m[6] ; q[1]~reg0 ; clk      ;
; N/A           ; None        ; -7.042 ns ; m[0] ; q[5]~reg0 ; clk      ;
; N/A           ; None        ; -7.097 ns ; m[0] ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; -7.098 ns ; m[0] ; q[6]~reg0 ; clk      ;
; N/A           ; None        ; -7.254 ns ; m[0] ; q[1]~reg0 ; clk      ;
; N/A           ; None        ; -7.537 ns ; m[4] ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; -7.537 ns ; m[4] ; q[2]~reg0 ; clk      ;
; N/A           ; None        ; -7.537 ns ; m[4] ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; -7.537 ns ; m[4] ; q[1]~reg0 ; clk      ;
; N/A           ; None        ; -7.603 ns ; m[5] ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; -7.603 ns ; m[5] ; q[2]~reg0 ; clk      ;
; N/A           ; None        ; -7.603 ns ; m[5] ; q[4]~reg0 ; clk      ;
; N/A           ; None        ; -7.603 ns ; m[5] ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; -7.603 ns ; m[5] ; q[1]~reg0 ; clk      ;
; N/A           ; None        ; -7.910 ns ; m[3] ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; -7.910 ns ; m[3] ; q[2]~reg0 ; clk      ;
; N/A           ; None        ; -7.910 ns ; m[3] ; q[1]~reg0 ; clk      ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Mar 16 10:42:51 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mchange100 -c mchange100 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 328.52 MHz between source register "q[2]~reg0" and destination register "q[0]~reg0" (period= 3.044 ns)
    Info: + Longest register to register delay is 2.780 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y11_N17; Fanout = 4; REG Node = 'q[2]~reg0'
        Info: 2: + IC(0.465 ns) + CELL(0.370 ns) = 0.835 ns; Loc. = LCCOMB_X33_Y11_N2; Fanout = 1; COMB Node = 'q[0]~166'
        Info: 3: + IC(0.378 ns) + CELL(0.589 ns) = 1.802 ns; Loc. = LCCOMB_X33_Y11_N0; Fanout = 7; COMB Node = 'q[0]~168'
        Info: 4: + IC(0.318 ns) + CELL(0.660 ns) = 2.780 ns; Loc. = LCFF_X33_Y11_N13; Fanout = 4; REG Node = 'q[0]~reg0'
        Info: Total cell delay = 1.619 ns ( 58.24 % )
        Info: Total interconnect delay = 1.161 ns ( 41.76 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.793 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X33_Y11_N13; Fanout = 4; REG Node = 'q[0]~reg0'
            Info: Total cell delay = 1.756 ns ( 62.87 % )
            Info: Total interconnect delay = 1.037 ns ( 37.13 % )
        Info: - Longest clock path from clock "clk" to source register is 2.793 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X33_Y11_N17; Fanout = 4; REG Node = 'q[2]~reg0'
            Info: Total cell delay = 1.756 ns ( 62.87 % )
            Info: Total interconnect delay = 1.037 ns ( 37.13 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "q[0]~reg0" (data pin = "m[0]", clock pin = "clk") is 9.238 ns
    Info: + Longest pin to register delay is 12.071 ns
        Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_79; Fanout = 2; PIN Node = 'm[0]'
        Info: 2: + IC(6.090 ns) + CELL(0.596 ns) = 7.621 ns; Loc. = LCCOMB_X33_Y10_N6; Fanout = 2; COMB Node = 'Add0~99'
        Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 7.707 ns; Loc. = LCCOMB_X33_Y10_N8; Fanout = 2; COMB Node = 'Add0~101'
        Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 7.793 ns; Loc. = LCCOMB_X33_Y10_N10; Fanout = 2; COMB Node = 'Add0~103'
        Info: 5: + IC(0.000 ns) + CELL(0.506 ns) = 8.299 ns; Loc. = LCCOMB_X33_Y10_N12; Fanout = 2; COMB Node = 'Add0~104'
        Info: 6: + IC(1.441 ns) + CELL(0.614 ns) = 10.354 ns; Loc. = LCCOMB_X33_Y11_N4; Fanout = 1; COMB Node = 'q[0]~165'
        Info: 7: + IC(0.369 ns) + CELL(0.370 ns) = 11.093 ns; Loc. = LCCOMB_X33_Y11_N0; Fanout = 7; COMB Node = 'q[0]~168'
        Info: 8: + IC(0.318 ns) + CELL(0.660 ns) = 12.071 ns; Loc. = LCFF_X33_Y11_N13; Fanout = 4; REG Node = 'q[0]~reg0'
        Info: Total cell delay = 3.853 ns ( 31.92 % )
        Info: Total interconnect delay = 8.218 ns ( 68.08 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.793 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X33_Y11_N13; Fanout = 4; REG Node = 'q[0]~reg0'
        Info: Total cell delay = 1.756 ns ( 62.87 % )
        Info: Total interconnect delay = 1.037 ns ( 37.13 % )
Info: tco from clock "clk" to destination pin "q[4]" through register "q[4]~reg0" is 8.184 ns
    Info: + Longest clock path from clock "clk" to source register is 2.793 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X33_Y11_N21; Fanout = 4; REG Node = 'q[4]~reg0'
        Info: Total cell delay = 1.756 ns ( 62.87 % )
        Info: Total interconnect delay = 1.037 ns ( 37.13 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.087 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y11_N21; Fanout = 4; REG Node = 'q[4]~reg0'
        Info: 2: + IC(1.841 ns) + CELL(3.246 ns) = 5.087 ns; Loc. = PIN_71; Fanout = 0; PIN Node = 'q[4]'
        Info: Total cell delay = 3.246 ns ( 63.81 % )
        Info: Total interconnect delay = 1.841 ns ( 36.19 % )
Info: th for register "q[0]~reg0" (data pin = "ld", clock pin = "clk") is 0.241 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.793 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X33_Y11_N13; Fanout = 4; REG Node = 'q[0]~reg0'
        Info: Total cell delay = 1.756 ns ( 62.87 % )
        Info: Total interconnect delay = 1.037 ns ( 37.13 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 2.858 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_90; Fanout = 8; PIN Node = 'ld'
        Info: 2: + IC(0.936 ns) + CELL(0.822 ns) = 2.858 ns; Loc. = LCFF_X33_Y11_N13; Fanout = 4; REG Node = 'q[0]~reg0'
        Info: Total cell delay = 1.922 ns ( 67.25 % )
        Info: Total interconnect delay = 0.936 ns ( 32.75 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Mar 16 10:42:52 2007
    Info: Elapsed time: 00:00:02