mchange100.map.eqn

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

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--A1L34Q is q[0]~reg0
A1L34Q = DFFEAS(A1L32, clk, !clr,  ,  ,  ,  , A1L21,  );


--A1L38Q is q[1]~reg0
A1L38Q = DFFEAS(A1L36, clk, !clr,  ,  ,  ,  , A1L21,  );


--A1L42Q is q[2]~reg0
A1L42Q = DFFEAS(A1L40, clk, !clr,  ,  ,  ,  , A1L21,  );


--A1L46Q is q[3]~reg0
A1L46Q = DFFEAS(A1L44, clk, !clr,  ,  ,  ,  , A1L21,  );


--A1L50Q is q[4]~reg0
A1L50Q = DFFEAS(A1L48, clk, !clr,  ,  ,  ,  , A1L21,  );


--A1L54Q is q[5]~reg0
A1L54Q = DFFEAS(A1L52, clk, !clr,  ,  ,  ,  , A1L21,  );


--A1L58Q is q[6]~reg0
A1L58Q = DFFEAS(A1L56, clk, !clr,  ,  ,  ,  , A1L21,  );


--A1L32 is q[0]~86
A1L32 = A1L34Q $ VCC;

--A1L33 is q[0]~87
A1L33 = CARRY(A1L34Q);


--A1L1 is add~224
A1L1 = m[0] $ VCC;

--A1L2 is add~225
A1L2 = CARRY(m[0]);


--A1L3 is add~226
A1L3 = m[1] & A1L2 & VCC # !m[1] & !A1L2;

--A1L4 is add~227
A1L4 = CARRY(!m[1] & !A1L2);


--A1L5 is add~228
A1L5 = m[2] & (GND # !A1L4) # !m[2] & (A1L4 $ GND);

--A1L6 is add~229
A1L6 = CARRY(m[2] # !A1L4);


--A1L7 is add~230
A1L7 = m[3] & A1L6 & VCC # !m[3] & !A1L6;

--A1L8 is add~231
A1L8 = CARRY(!m[3] & !A1L6);


--A1L9 is add~232
A1L9 = m[4] & (GND # !A1L8) # !m[4] & (A1L8 $ GND);

--A1L10 is add~233
A1L10 = CARRY(m[4] # !A1L8);


--A1L11 is add~234
A1L11 = m[5] & A1L10 & VCC # !m[5] & !A1L10;

--A1L12 is add~235
A1L12 = CARRY(!m[5] & !A1L10);


--A1L13 is add~236
A1L13 = m[6] $ A1L12;


--A1L17 is Equal~64
A1L17 = A1L13 & A1L58Q & (A1L34Q $ !A1L1) # !A1L13 & !A1L58Q & (A1L34Q $ !A1L1);


--A1L18 is Equal~65
A1L18 = A1L50Q & A1L9 & (A1L54Q $ !A1L11) # !A1L50Q & !A1L9 & (A1L54Q $ !A1L11);


--A1L19 is Equal~66
A1L19 = A1L38Q & A1L3 & (A1L42Q $ !A1L5) # !A1L38Q & !A1L3 & (A1L42Q $ !A1L5);


--A1L20 is Equal~67
A1L20 = A1L46Q $ A1L7;


--A1L21 is Equal~68
A1L21 = A1L17 & A1L18 & A1L19 & !A1L20;


--A1L36 is q[1]~88
A1L36 = A1L38Q & !A1L33 # !A1L38Q & (A1L33 # GND);

--A1L37 is q[1]~89
A1L37 = CARRY(!A1L33 # !A1L38Q);


--A1L40 is q[2]~90
A1L40 = A1L42Q & (A1L37 $ GND) # !A1L42Q & !A1L37 & VCC;

--A1L41 is q[2]~91
A1L41 = CARRY(A1L42Q & !A1L37);


--A1L44 is q[3]~92
A1L44 = A1L46Q & !A1L41 # !A1L46Q & (A1L41 # GND);

--A1L45 is q[3]~93
A1L45 = CARRY(!A1L41 # !A1L46Q);


--A1L48 is q[4]~94
A1L48 = A1L50Q & (A1L45 $ GND) # !A1L50Q & !A1L45 & VCC;

--A1L49 is q[4]~95
A1L49 = CARRY(A1L50Q & !A1L45);


--A1L52 is q[5]~96
A1L52 = A1L54Q & !A1L49 # !A1L54Q & (A1L49 # GND);

--A1L53 is q[5]~97
A1L53 = CARRY(!A1L49 # !A1L54Q);


--A1L56 is q[6]~98
A1L56 = A1L58Q $ !A1L53;


--clk is clk
--operation mode is input

clk = INPUT();


--clr is clr
--operation mode is input

clr = INPUT();


--m[6] is m[6]
--operation mode is input

m[6] = INPUT();


--m[5] is m[5]
--operation mode is input

m[5] = INPUT();


--m[4] is m[4]
--operation mode is input

m[4] = INPUT();


--m[3] is m[3]
--operation mode is input

m[3] = INPUT();


--m[2] is m[2]
--operation mode is input

m[2] = INPUT();


--m[1] is m[1]
--operation mode is input

m[1] = INPUT();


--m[0] is m[0]
--operation mode is input

m[0] = INPUT();


--q[0] is q[0]
--operation mode is output

q[0] = OUTPUT(A1L34Q);


--q[1] is q[1]
--operation mode is output

q[1] = OUTPUT(A1L38Q);


--q[2] is q[2]
--operation mode is output

q[2] = OUTPUT(A1L42Q);


--q[3] is q[3]
--operation mode is output

q[3] = OUTPUT(A1L46Q);


--q[4] is q[4]
--operation mode is output

q[4] = OUTPUT(A1L50Q);


--q[5] is q[5]
--operation mode is output

q[5] = OUTPUT(A1L54Q);


--q[6] is q[6]
--operation mode is output

q[6] = OUTPUT(A1L58Q);